The formation of polycrystalline-Si thin-film transistors with a thinned channel layer

Abstract

Polycrystalline-Si thin-film transistors with a thinned channel layer have been examined. A thinner channel layer may yield a larger on-state current, due to better gate control over the entire channel region. In addition, a thinned channel layer can also reduce the source/drain bulk punch-through and thus the lateral electric field within the channel region. As a result, a 20 nm thick channel layer can significantly suppress the leakage current at relatively large negative gate voltages better than the 100 nm thick channel layer. However, a thinner channel layer would lead to more bending of the energy band at an applied gate voltage, thus enhancing the vertical electric field. Accordingly, when a channel length of 1 µm is examined, the 20 nm thick channel layer would resultantly cause a lowest leakage current (off-state current) value a half-order larger than the 100 nm thick channel layer. Hence, from the device aspect, a properly thinned channel layer, which is of 30 nm thickness here, can be employed to achieve a large on-state current without considerable degradation of the off-state leakage current, while suppressing the leakage current induced at relatively high negative gate voltages.