Channel width effect on the operation of 4H-SiC vertical JFETs

Abstract

SiC JFETs may have the lowest overall losses of switching devices and can operate at temperatures over 400 °C. Over different junction field-effect transistor (JFET) designs, the trenched and implanted (TI) gate vertical JFET (TI-VJFET) is very attractive since it may have the lowest on-resistance and its fabrication does not require epitaxial overgrowth or multiple angled implantation. 4H-SiC TI-VJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. Different design factors, including channel width, channel length, and mesa height, are considered. The effect of the channel geometry on the electrical characteristics has been studied by varying their width (1.5–5 µm). The specific ON resistance (RON) of the fabricated devices, at VGS = 0 V, varied from 12.5 to 6.2 mΩ cm2 with increasing the channel width. The effect of the channel width was more tremendous on the breakdown voltage of the transistors passing from 80 to 500 V, showing the importance of the static-induction effect (saddle point potential influenced by drain potential) on the transistor blocking characteristics. Indeed, the blocking voltage gain is varying from 50 to single digit values when increasing the channel width. The physical reason is that the blocking gain to first order depends exponentially on the channel dimensions as the drain-source current is exponentially related to the saddle point potential.