Verilog-A Code Research Articles

Building an Analog Circuit Synapse for Deep Learning Neuromorphic Processing

In this article, we propose a circuit to imitate the behavior of a Reward-Modulated spike-timing-dependent plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness in the shared synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130 nm process. The article’s main goal is to provide the basic building blocks for deep neural networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity.

Surface-Potential-Based Compact Modeling of p-GaN Gate HEMTs.

We propose a surface potential (SP)-based compact model of p-GaN gate high electron mobility transistors (HEMTs) which solves the Poisson equation. The model includes all possible charges in the GaN channel layer, including the unintended Mg doping density caused by out-diffusion. The SP equation and its analytical approximate solution provide a high degree of accuracy for the SP calculation, from which the closed-form I–V equations are derived. The proposed model uses physical parameters only and is implemented in Verilog-A code.

Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

In this article, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for different channel lengths with a single set of parameters. Also, we build a model for terminal charges of NC-NSFET using the core model and the earlier developed inner fringing charge model. Using our physics-based model, we find that quasi ballistic transport worsens the capacitance matching in NCFET compared to drift-diffusion only case. We validate the compact model for the drain current and the terminal charges with the TCAD results. The proposed compact model is computationally efficient and implemented in the Verilog-A code to enable SPICE circuit simulations. Finally, we demonstrate this by applying our model for NC-NSFET based CMOS inverter and SRAM circuit implementations in SPICE.

Parameter Extraction for the PSPHV LDMOS Transistor Model

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method is verified on devices from different technologies. Verilog-A code for PSPHV is publicly available.

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed. The conventional 6T TFET SRAM cell is designed using DG TFET of 30 nm. For the circuit simulation, the symbol of DG TFET is developed with the help of a look-up table based Verilog-A code. The radiation induced single event upset (SEU) causes a change in the stored data of SRAM cell. In order to improve the SEU sensitivity, the radiation hardening-by-design technique (RHBD) is introduced in 6T TFET SRAM cell by connecting the RC feedback loop between the two cross coupled inverters. The standby power of the TFET SRAM cell is calculated and compared before and after the radiation mitigation technique insertion.

A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects

In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ([Formula: see text]), transconductance ([Formula: see text]), gate to drain capacitance ([Formula: see text]) and gate to source capacitance ([Formula: see text]) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than [Formula: see text] NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.

Compact Modeling of Perpendicular STT-MTJs With Double Reference Layers

This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) with double-barrier and two antiparallel reference layers (DMTJs). The approach is based on a Verilog-A analytical compact model that properly takes into account the effect of the DMTJ physical stack on both resistance and statistical switching characteristics. Validation results demonstrate a good agreement of analytical calculations with both numerical simulations and experimental data. To test the functionality of the developed Verilog-A code in hybrid CMOS/STT-MTJ circuit simulations, we have investigated the performance of a non-volatile flip-flop (NVFF) implemented with DMTJs and FinFETs in comparison with its single-barrier MTJ (SMTJ)-based counterpart. The reduced switching current of DMTJs allows reducing the backup time and energy by a factor of 3X and 6.1X, respectively. Such benefits are obtained along with smaller area occupation and better performance in the flip-flop (FF) active operation mode.

RRAM Device Models: A Comparative Analysis With Experimental Validation

Resistive Random Access Memories (RRAM) have recently shown outstanding characteristics such as high-scalability, high-speed, high-density, and low-energy operation. A simple and accurate model is crucial for rapid design and verification when using RRAM devices at the circuit level. The appropriate model selection gives insight into the behavior of RRAM as well as the efficient use of its unique properties. This work intends to guide the circuit designers in selecting the most appropriate RRAM model for their applications. We introduce a complete set of evaluation criteria for memristor models: type of model, type of switching, genericity, complexity, compatibility with actual physical switching mechanisms, linearity, symmetry, voltage/current control, hard set/soft reset, support electroforming, support for high programming signal frequencies, existence of a threshold, voltage level, timing dependence, temperature dependence and variability. This study compares the main existing RRAM models and summarizes the results in a table showing the main features and limitations of each model. Through extensive simulations and comparisons with experimental data, we provide an analysis and a validation of the reviewed models within the same simulation environment, ranging from individual elementary cells to large memory arrays. Furthermore, we provide a single and unique Verilog-A code integrating all the compared models.

A Comprehensive High-Level Model for CMOS-MEMS Resonators

This paper presents a behavioral modeling technique for CMOS microelectromechanical systems (MEMS) microresonators that enables simulation of an MEMS resonator model in Analog Hardware Description Language format within a system-level circuit simulation. A 100-kHz CMOS-MEMS resonant pressure sensor has been modeled into Verilog-A code and successfully simulated within Cadence framework. Analysis has shown that simulation results of the reported model are in agreement with the device characterization results. As an application of the proposed methodology, simulation and results of the model together with an integrated monolithic low-noise amplifier is exemplified for detecting the position change of the resonator.

JFETIDG: A Compact Model for Independent Dual-Gate JFETs With Junction or MOS Gates

This paper presents the details of JFETIDG, a compact model for independent dual-gate junction field-effect transistors with any combination of p-n junction or MOS gates. JFETIDG accounts for nonlinearity from depletion pinching, velocity saturation, and self-heating, and includes extensive modeling of geometry and temperature dependences, parasitics, noise, and statistical variations. We also demonstrate that it accurately models long channel junctionless MOS transistors. The model is verified by comparison with TCAD simulations and experimental data. Verilog-A code for JFETIDG is available in the public domain.

Performance analysis of InAs- and GaSb-InAs-based independent gate tunnel field effect transistor RF mixers

This study compares the performance of radio frequency (RF) mixers employing independent-gate tunnel field-effect transistors (IG TFETs) based on homo (InAs) and heterojunctions (GaSb-InAs). A RF mixer circuit using double gate TFET of 20 nm is designed with the optimal biases on the two gates. IG TFETs used in the circuit simulation are developed with the help of a look-up table based Verilog-A code. The down conversion of RF mixers are operated at a frequency of 95 GHz. The figures-of-merit (FOM), conversion gain $$(G_{\mathrm {C}})$$ , noise figure (NF) and the average power consumption of the mixer circuits are studied along with the different device parameter variations, gate length $$(L_{\mathrm {g}})$$ , gate oxide thickness $$(T_{\mathrm {ox}})$$ and channel thickness $$(T_{\mathrm {ch}})$$ . Higher $$G_{\mathrm {C}}$$ and lower NF are achieved for heterojunction-based TFET mixers with respect to their parameter variations. An average power consumption of 168 and $$227.5\,{\upmu }\hbox {W}$$ is obtained for homo- and heterojunction-based TFET mixers, respectively.

A new compact model for bipolar RRAMs based on truncated-cone conductive filaments—a Verilog-A approach

A new model for bipolar resistive random-access memories (RRAMs) is presented in this article. Redox and diffusion processes are used to describe in detail the physics behind the filamentary resistive switching (RS) mechanisms of the RRAMs under study. The model includes truncated-cone shaped filaments which are known to be close to the real conductive filament (CF) geometry and a detailed thermal approach, where two temperatures are considered to describe the rupture process at the CF’s narrowest part and also the main CF body’s electrical conductivity variations. Ti/ZrO2/Pt RRAM devices have been fabricated and measured, and the model has allowed us to reproduce the experimental data for all the cases analyzed. Finally, the model has been implemented in Verilog-A code within the ADS circuit simulator, and the response of a device to pulsed external voltages within a characterization circuit has been simulated, producing good results when compared with experimental measurements.

A compact model and direct parameters extraction techniques For amorphous gallium-indium-zinc-oxide thin film transistors

An advanced compact and analytical drain current model for the amorphous gallium indium zinc oxide (GIZO) thin film transistors (TFTs) is proposed. Its output saturation behavior is improved by introducing a new asymptotic function. All model parameters were extracted using an adapted version of the Universal Method and Extraction Procedure (UMEM) applied for the first time for GIZO devices in a simple and direct form. We demonstrate the correct behavior of the model for negative VDS, a necessity for a complete compact model. In this way we prove the symmetry of source and drain electrodes and extend the range of applications to both signs of VDS.The model, in Verilog-A code, is implemented in Electronic Design Automation (EDA) tools, such as Smart Spice, and compared with measurements of TFTs. It describes accurately the experimentalcharacteristics in the whole range of GIZO TFTs operation,making themodelsuitable for the design of circuits using these types of devices.

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation.

Electrical Compact Modeling of Graphene Base Transistors

Following the recent development of the Graphene Base Transistor (GBT), a new electrical compact model for GBT devices is proposed. The transistor model includes the quantum capacitance model to obtain a self-consistent base potential. It also uses a versatile transfer current equation to be compatible with the different possible GBT configurations and it account for high injection conditions thanks to a transit time based charge model. Finally, the developed large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using advanced numerical simulation.

A complete and Verilog-A compatible Gate-All-Around long-channel junctionless MOSFET model implemented in CMOS inverters

In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A code, which will be further used in commercial circuit simulators. The model in Verilog-A is integrated in the SmartSpice circuit simulator and tested in a CMOS inverter. Both p-channel and n-channel device models are validated. Also, the results are compared with data from 3D numerical simulations, showing a very good agreement in all transistors׳ operation regimes.

Simulation of Organic Thin Film Transistor at both Device and Circuit Levels

Organic materials and devices are gaining more and more attention in microelectronics. They are dedicated to low cost applications and easy fabrication. Organic thin film transistors (OTFTs) are now making significant inroads into many new large-area applications, considering that they can be fabricated at low temperatures and with high throughput on a wide range of unconventional substrates, such as glass, plastic, fabric, and paper. In this paper an OTFT model is used in cadence, a Verilog-a code is written and used to create an OTFT device. This is done so that OTFT circuits can be simulated before fabrication. First, the model is validated by characterizing the device, showing its FET characteristics. Second, the device is used inside a circuit, and the circuit performance is analyzed. Inverter circuit is implemented using the modelled OTFT device, transfer characteristics, input and output waveforms are drawn using the simulation tool. The transistors used have 10m/20u W/L ratio, the inverter is used at 1 kHz frequency.

Scalable Electrical Compact Modeling for Graphene FET Transistors

A new scalable electrical compact model for the Graphene FET devices is proposed. Starting from Thiele's quasianalytical model, the equations are modified to be fully compatible with SPICE-like circuit simulation. Compared to Meric et al. model, the charge model is improved. This large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using different measurements from the literature, and furthermore, its scalability is demonstrated.

A Verilog-A model for silicon nanowire biosensors: From theory to verification

Silicon nanowires offer great potential as highly sensitive biosensors. Since the signals they produce are quite weak and noisy, the use of integrated circuits is preferable to read out and digitize these signals as quickly as possible following the sensing event to take full advantage of the properties of the nanowires. In order to design optimized and tailored circuits, simulations involving the sensor itself in the design phase are needed.We propose here a Verilog-A model for silicon nanowire-based biosensors. The model can easily be applied using commercially available electronic design automation (EDA) tools that are commonly used for integrated circuit design and simulations. The model is quite general and comprehensive; it can be used to simulate different types of sensing events, while still being quite simple and undemanding in terms of computational power.The model is described in detail and verified with measurements from two different nanowire sensors featuring aluminum-oxide and hafnium-oxide coatings. Good agreement has been achieved in all cases, with errors never exceeding 21%.The complete Verilog-A code is made available in the Appendix.

Symmetrical unified compact model of short-channel double-gate MOSFETs

An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.