Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

Amol D Gaidhane,Yogesh Singh Chauhan,Girish Pahwa,Avirup Dasgupta,Amit Verma

doi:10.1109/jeds.2020.3019927

Abstract

In this article, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for different channel lengths with a single set of parameters. Also, we build a model for terminal charges of NC-NSFET using the core model and the earlier developed inner fringing charge model. Using our physics-based model, we find that quasi ballistic transport worsens the capacitance matching in NCFET compared to drift-diffusion only case. We validate the compact model for the drain current and the terminal charges with the TCAD results. The proposed compact model is computationally efficient and implemented in the Verilog-A code to enable SPICE circuit simulations. Finally, we demonstrate this by applying our model for NC-NSFET based CMOS inverter and SRAM circuit implementations in SPICE.

Highlights

Beyond 7nm technology node, owing to significantly large short channel effects (SCEs), the state-of-the-art FinFET devices may have to be eventually replaced by the geometries with a superior gate controllability such as nanosheet and nano-wire FETs [1]–[3]
We have developed a compact model for NC-Nanosheet FET (NSFET) including quasi ballistic transport for sub-7nm technology node using the L-K model of ferroelectric material
We have demonstrated that the quasi-ballistic transport can reduce the voltage amplification effect in very short channel NCFETs

Summary

INTRODUCTION

Beyond 7nm technology node, owing to significantly large short channel effects (SCEs), the state-of-the-art FinFET devices may have to be eventually replaced by the geometries with a superior gate controllability such as nanosheet and nano-wire FETs [1]–[3]. The fringing field effect in a short channel NCFET has been found to significantly lower the steady-state leakage of the device, which can help in continuing Dennard’s scaling for the CMOS devices, i.e., increasing the frequency of the processor with every new technology node [8]–[10]. Ferroelectric NC based gate all around FET is expected to be a suitable candidate for futuristic ultra-scaled channel devices. We develop a VerilogA implementable compact model for sub-7nm NC-NSFET using the Landau-Khalatnikov (L-K) equation for the ferroelectric layer.

TCAD SIMULATION FRAMEWORK

CONCLUSION