Ultrathin Gate Dielectrics Research Articles

The role of Si orientation and temperature on the carrier mobility in metal oxide semiconductor field-effect transistors with ultrathin HfO2 gate dielectrics

The effective carrier mobility in HfO2-based n- and p-metal oxide semiconductor field-effect transistors and in their control SiO2 devices has been investigated as a function of temperature for three different silicon crystal orientations (100), (111), and (110). For both HfO2 and SiO2, the electron mobility is steadily reduced between these orientations, whereas the hole mobility exhibits the opposite trend. The mobility-temperature dependence follows a power law μ∼μoTα, and the exponent α varies also systematically with Si orientation and carrier type. The main finding is the presence of two temperature ranges with specific exponent values α1 and α2 occurring only for holes and for the (100) and (111) orientations. This crossover with rising temperature is explained by the progressive scattering of Si light holes that form the first excited states above the heavy-hole ground state. The same observation in SiO2∕Si(100) points to scattering by acoustic phonons in bulk Si. In addition to the contribution of acoustic phonons, the systematic reduction of mobility in HfO2 devices as compared to SiO2 is attributed to remote soft optical phonon scattering. A detailed analysis allows us to determine the precise inversion charge density range (or effective electric field) where remote phonon scattering predominates.

Ultrathin HfOxNy Gate Insulator Formation by Electron Cyclotron Resonance Ar/N2 Plasma Nitridation of HfO2 Thin Films

HfO x N y thin films formed by the electron cyclotron resonance (ECR) Ar/N 2 plasma nitridation of HfO 2 films were investigated for high-k gate insulator applications. HfO x N y thin films formed by the ECR Ar/N 2 plasma nitridation (60s) of 1.5-nm-thick HfO 2 films, which were deposited on chemically oxidized Si(100) substrates, were found to be effective for suppressing interfacial layer growth or crystallization during postdeposition annealing (PDA) in N 2 ambient. After 900°C PDA of for 5 min in N 2 ambient, it was found that HfSiON film with a relatively high dielectric constant was formed on the HfO x N y /Si interface by Si diffusion. An equivalent oxide thickness (EOT) of 2.0 nm and a leakage current density of 1.0 x 10 -3 A/cm 2 (at V FB - 1 V) were obtained. The effective mobility of the fabricated p-channel metal-insulator-semiconductor field-effect transistor (MISFET) with the HfO x N y gate insulator was 50 cm 2 /Vs, and the gate leakage current of the MISFET with the HfO x N y gate insulator was found to be well suppressed compared with the MISFET with the HfO 2 gate insulator after 900°C PDA because of the nitridation of HfO 2 .

Influence of bulk bias on negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin SiON gate dielectrics

Bulk (well) bias effects (grounded, positively biased, and floating) on both static and dynamic negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin SiON gate dielectrics were systematically investigated. The device degradation under both static and dynamic negative bias temperature (NBT) stresses with relatively large gate voltage (Vg) is significantly enhanced by a positive bulk bias (Vb). Moreover, the device degradation under bipolar pulsed bias temperature (BT) stress is dramatically enhanced by floating the bulk electrode. Both phenomena can be attributed to an additional degradation related to hot hole injection. The holes are energized by an electrical field of the induced depletion region between channel and bulk provided by the positive Vb or, in the case of bipolar pulsed BT stress with the bulk electrode floating, by the transient depletion region below the channel induced by the p-n junction between source (drain) and bulk upon the gate voltage Vg being switched from positive to negative with a transition time less than about 0.2–100ms.

Excellent electrical and reliability characteristics of 11Å oxynitride gate dielectrics by remote plasma nitridation treatment

Ultrathin oxynitride gate dielectrics of similar thickness (∼1.1nm) fabricated by a rapid thermal NO-nitrided oxide (RTNO), a RTNO with remote plasma nitridation (RPN) treatment (RTNO-RPN), an in situ steam generated (ISSG) NO oxide, and an ISSG with RPN treatment (ISSG-RPN) are investigated. The results demonstrate that ISSG-RPN gate dielectrics exhibit superior interface properties, reduced leakage current, and improved reliability compared to other gate dielectrics. The ISSG-RPN oxynitride film is an attractive candidate as the advanced gate dielectrics in future generations of ultralarge scale integration complementary metal-oxide semiconductor technologies.

Electrical Characterization of 13 A In Situ Steam-Generated Oxynitride Gate Dielectrics

Ultrathin oxynitride gate dielectrics of similar thickness (∼1.3 nm) processed by an in situ steam-generated (ISSG), an ISSG with NO rapid thermal processing (RTP) treatment (ISSG-NO), and an ISSG with O 2 RTP treatment (ISSG-O 2 ) are investigated. The results demonstrate that ISSG-NO gate dielectrics exhibit superior interface properties, reduced leakage current, and improved reliability compared to other gate dielectrics. The ISSG-NO oxynitride film is an attractive candidate as the gate dielectrics in 90 nm and possibly beyond for complementary metal oxide semiconductor technologies.

Capacitance–Voltage Measurement Method for Ultrathin Gate Dielectrics Using LC Resonance Circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.

Effect of thickness on the crystallization of ultrathin HfSiON gate dielectrics

The crystallization of ultrathin hafnium silicon oxynitride (HfSiON) gate dielectric is studied as a function of physical thickness. Grazing incidence x-ray diffraction (GI-XRD) was used to detect phase separation and crystallization of 1.5, 2.0, 2.5, and 4.0 nm HfSiON films after 1000°C10s dopant activation anneal. Crystallization peaks corresponding to monoclinic and tetragonal HfO2 were detected in 2.5 and 4.0 nm HfSiON films. These GI-XRD results were supported by plan-view transmission electron microscopy images of the HfSiON films. Film crystallinity seems to impact voltage instability in thicker HfSiON films.

Quantum charge transportation in metal-oxide-Si structures with ultrathin oxide

Quantum electron dynamics in metal-oxide-silicon structures with ultrathin oxide is calculated. A linear model of the surface-potential energy is used in the calculation. This treatment simplifies the computation for both the interface potential and the field penetration distance in the substrate. The electronic metastable states induced by the internal field penetration in the substrate and the running states in the gate region are then treated separately, with a weak condition for the continuity of the probability density at the substrate-dielectric interface. The probability current in the gate and then the total tunneling current are obtained for different gate voltages. While the spectrum of the transverse energy in the metastable states is assumed as continuous, the emerging probability current is shown to vanish for a finite number of values of the transverse energy, which may be interpreted as standing (bound) states in the structure. This model yields excellent fittings for the experimental data obtained from metal-oxide-semiconductor structures with different ultrathin gate dielectrics.

Structural and electrical characterizations of ultrathin HfO2 gate dielectrics treated by nitrogen-plasma atmosphere

Ultrathin HfO2 gate dielectrics with 3.00 and 2.60nm thicknesses were prepared at 300°C by plasma-enhanced metal-organic chemical-vapor deposition. These HfO2 films were treated by N2 plasma at 300°C, and exhibit not only an excellent smooth surface morphology but also higher crystallization temperature and improved electrical properties. The N2-plasma treatment did not influence the interface charge density of the films. The 2.6nm HfO2 treated by N2 plasma showed a leakage current density of 3×10−3A∕cm2 at −1.5V, equivalent oxide thickness of 1.24nm, and flatband voltage of 2mV. We find that N2-plasma treatment in Hf-based ultrathin gate dielectrics can improve the electrical properties, as well as thermal stability.

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.

Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

The interface trap generation (ΔNit) and fixed oxide charge buildup (ΔNot) under negative bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current–current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for ΔNit and ΔNot. At the earlier stress times, ΔNit dominates the threshold voltage shift (ΔVth) and ΔNot is negligible. With increasing stress time, the rate of increase of ΔNit decreases continuously, showing a saturating trend for longer stress times, while ΔNot still has a power-law dependence on stress time so that the relative contribution of ΔNot increases. The thermal activation energy of ΔNit and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.

Parameter extraction using novel phenomena in nano-MOSFETs with ultra-thin (EOT = 0.46–1.93 nm) high-K gate dielectrics

Novel features of and a new technique for parameter extraction are outlined here for MOS devices with ultra-thin high-K MOS devices. These parameters include the channel doping density, the doping density profile, and the flat-band voltage—all very important for the high-K technology, besides the surface potential, the gate dielectric capacitance, and the accumulation surface potential quotient. The reliability of the new technique was confirmed by comparison with the results from other techniques. The experimental results indicate diffusion of metal impurities into the channel region during the device processing.

Reliability Scaling Limit of 14-Å Oxynitride Gate Dielectrics by Different Processing Treatments

Various ultrathin oxynitride gate dielectrics of similar thickness processed by a rapid thermal NO-nitrided oxide (RTNO), a remote plasma nitrided oxide (RPN), a remote plasma nitridation of oxide with rapid thermal NO annealing , and a rapid thermal reoxidation of remote plasma nitrided oxide (ReoxRPN) are reported for the first time as a means to extend the reliability scaling limit of /oxynitride-based gate dielectrics. The gate dielectric films show superior interface properties, significantly reduced leakage current, and improved reliability compared to other gate dielectrics fabricated by different processes.

Electrical properties of ultrathin HfO2 films for replacement metal gate transistors, fabricated by atomic layer deposition using Hf(N(CH3)(C2H5))4 and O3

Ultrathin HfO2 gate dielectric was fabricated by atomic layer deposition (ALD) technology using tetrakis(ethylmethylamino)hafnium {Hf[N(CH3)(C2H5)]4}, with O3 as an oxidant for use in replacement metal gate transistors. From secondary ion mass spectrometry analyses, the ALD process temperature was very important for the fabrication of high-quality HfO2 films. The dielectric constant with 275 °C deposition was higher than that at 200–250 °C. Furthermore, the VFB with 200 °C deposition was about 0.1–0.15 V lower than that at 275 °C, due to formation of high residual impurity concentrations, such as carbon, in the HfO2 films. The leakage current densities in the 275 °C case were reduced by about five orders with respect to reference SiO2 films. From these results, it was judged that the ALD process temperature of 275 °C was suitable for the fabrication of ultrathin HfO2 gate dielectrics necessary to improve the leakage current characteristics.

Organic Nanodielectrics for Low Voltage Carbon Nanotube Thin Film Transistors and Complementary Logic Gates

We report the implementation of three dimensionally cross-linked, organic nanodielectric multilayers as ultrathin gate dielectrics for a type of thin film transistor device that uses networks of single-walled carbon nanotubes as effective semiconductor thin films. Unipolar n- and p-channel devices are demonstrated by use of polymer coatings to control the behavior of the networks. Monolithically integrating these devices yields complementary logic gates. The organic multilayers provide exceptionally good gate dielectrics for these systems and allow for low voltage, low hysteresis operation. The excellent performance characteristics suggest that organic dielectrics of this general type could provide a promising path to SWNT-based thin film electronics.

A Novel Methodology for Sensing the Breakdown Location and Its Application to the Reliability Study of Ultrathin Hf-Silicate Gate Dielectrics

In this paper, we propose a new methodology for sensing the breakdown location along the channel length with the MOSFET biased in the inversion regime. The usefulness of this technique is demonstrated in the characterization of ultrathin Hf-silicate gate dielectrics breakdown. Two different breakdown modes are deconvoluted: an initial progressive breakdown in the channel with a degradation rate strongly dependent on the applied voltage and a successive hard-breakdown at source and drain extensions, which more impacts the device reliability.

Voltage acceleration of time-dependent breakdown of ultra-thin gate dielectrics

Experimental results support the power-law model to correctly describe the voltage acceleration of time-dependent dielectric breakdown (TDDB) in an oxide thickness range where direct tunnelling of electrons is the primary leakage mechanism. The accessible experimental time range to prove a certain voltage acceleration behaviour is compared to the time range that needs to be covered during a projection to use conditions. Further, the problem of correct gate oxide breakdown detection in PFET devices is discussed, because it strongly affects the determination of time to breakdown, Weibull slope, acceleration model, and acceleration factor.

Positive Bias Temperature Instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics

Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate dielectrics has been investigated. We propose that PBTI is due to electron trapping in the high-k dielectrics layer and we present results of measurements performed at different bias condition and temperatures consistent with the proposed model. Extrapolated lifetimes indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices only in the case of Hf rich-layers.

Study of breakdown in ultrathin gate dielectrics using constant voltage stress and successive constant voltage stress

A comparative study on understanding the effect of conventional constant voltage stress (CVS) and successive constant voltage stress (SCVS) methodology on the post-breakdown transistor performance has been performed. In CVS stressing methodology, breakdowns in ultrathin gate oxides in narrow MOSFETs in moderate and high compliance current, Igl, range are usually associated with the formation of dielectric-breakdown-induced epitaxy (DBIE). Whereas in SCVS, due to a more controlled thermal environment in narrow MOSFET, DBIE is hardly found for breakdowns stressed under a similar Igl (as that of CVS in the moderate Igl) and gate oxide thickness. On the other hand, for both CVS and SCVS, once the DBIE is nucleated during progressive breakdown, its growth results in substantial gate dielectric thinning which is one of the mechanisms responsible for enhanced device degradation.

Dielectric-breakdown-induced epitaxy: a universal breakdown defect in ultrathin gate dielectrics

The breakdown phenomena in SiO/sub x/N/sub y/ (EOT=20 /spl Aring/) gate dielectric under a two- stage constant voltage stress in inversion mode are physically analyzed with the aid of transmission electron microscopy. The results show that dielectric-breakdown-induced epitaxy (DBIE) remains as one of the major failure defects responsible for gate dielectric breakdown evolution even for a stress voltage as low as 2.5 V. Based on the results, the same failure mechanism i.e., presence of DBIE would be responsible for the degradation in ultrathin gate dielectrics for gate voltage below 2.5 V. It is believed that DBIE will be present in MOSFETs failed at nominal operating voltage.