Abstract
A comparative study on understanding the effect of conventional constant voltage stress (CVS) and successive constant voltage stress (SCVS) methodology on the post-breakdown transistor performance has been performed. In CVS stressing methodology, breakdowns in ultrathin gate oxides in narrow MOSFETs in moderate and high compliance current, Igl, range are usually associated with the formation of dielectric-breakdown-induced epitaxy (DBIE). Whereas in SCVS, due to a more controlled thermal environment in narrow MOSFET, DBIE is hardly found for breakdowns stressed under a similar Igl (as that of CVS in the moderate Igl) and gate oxide thickness. On the other hand, for both CVS and SCVS, once the DBIE is nucleated during progressive breakdown, its growth results in substantial gate dielectric thinning which is one of the mechanisms responsible for enhanced device degradation.
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