Ultrathin Gate Dielectrics Research Articles

Impact of New Approach to Improve MOSFETs Performance with Ultrathin Gate Insulator

In this study, we focus on the difference behavior of the gate-channel capacitance (Cgc) characteristics in the inversion-mode (IM) and the accumulation-mode (AM) SOI MOSFETs. We experimentally demonstrate that the gate-channel capacitance in the AM MOS device is obviously larger than that in IM MOS device using the same gate insulator on the same wafer. The increase of the Cgc in AM MOSFETs is much more remarkable as downscaling the gate insulator due to the different inversion and accumulation layer quantization effect and poly-Si gate depletion effect. As the result, the current drivability has been obviously improved in the AM MOSFETs resulted from its vastly increased gate-channel capacitance, especially in the MOSFETs with the ultrathin gate insulator.

Impact of New Approach to Improve MOSFETs Performance with Ultrathin Gate Insulator

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Threshold Voltage of Ultrathin Gate-Insulator MOSFETs

This letter elucidates the difficulties in applying the conventional 2psi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> threshold voltage model for current MOSFETs with ultrathin gate insulator and presents a new comprehensive alternative for general MOSFETs. After high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectric is successfully developed to acquire a strong gate control, the on-off switching of MOSFETs is no longer dependent on substrate doping concentration as before. A physical drift-current threshold voltage model is proposed directly from the drain current itself, where the threshold voltage is defined as the onset of the drift current playing the main contribution in the total drain current. It can properly predict threshold voltage for general MOSFET devices and appropriately provide a physical current criterion for extracting the threshold voltage.

Characterization for High-Performance CMOS Using In-Wafer Advanced Kelvin-Contact Device Structure

In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current-voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method.

Electrical characteristics of metal-oxide-semiconductor capacitors on p-GaAs using atomic layer deposition of ultrathin HfAlO gate dielectric

Properties of ultrathin HfAlO gate dielectrics on sulfur-passivated p-GaAs were investigated using capacitance-voltage and current-voltage measurement techniques and angle-resolved x-ray photoelectron spectroscopy. By optimizing the individual layer thickness of atomic-layer deposited Al2O3 and HfO2 and the postdeposition anneal (PDA) conditions, a low equivalent oxide thickness of 1.6 nm, low gate leakage of 2.6×10−3 A/cm2 at Vg=Vfb−1 V, and excellent frequency dispersion characteristics were obtained. No interfacial As–O bonding and only a small amount of Ga–O bonding were detected after PDA at 500 °C. These results reveal a good quality dielectric interface on GaAs without an additional interface passivation layer.

Defect Tolerance and Nanomechanics in Transistors that Use Semiconductor Nanomaterials and Ultrathin Dielectrics

AbstractThis paper describes experimental and theoretical studies of the mechanics of free‐standing nanoribbons and membranes of single‐crystalline silicon transfer printed onto patterned dielectric layers. The results show that analytical descriptions of the mechanics agree well with experimental data, and they explicitly reveal how the geometry of dielectric layers (i.e., the width and depth of the features of relief) and the silicon (i.e., the thickness and widths of the ribbons) affect mechanical bowing (i.e., “sagging”) in the suspended regions of the silicon. This system is of practical importance in the use of semiconductor nanomaterials for electronic devices, because incomplete sagging near defects in gate dielectrics provides a level of robustness against electrical shorting in those regions which exceeds that associated with conventional deposition techniques for thin films. Field effect transistors formed using silicon nanoribbons transferred onto a range of ultrathin gate dielectrics, including patterned epoxy, organic self‐assembled monolayers, and HfO2, demonstrate these concepts.

Pre-atomic layer deposition surface cleaning and chemical passivation of (100) In0.2Ga0.8As and deposition of ultrathin Al2O3 gate insulators

We have developed and tested the efficacy of a method for pre-atomic layer deposition (ALD) surface preparation that removes native oxides from the (100) In0.2Ga0.8As surface and provides a clean starting surface for ALD of ultrathin Al2O3 layers. Successive wet etching by aqueous HCl and NH4(OH) solutions and in situ pre-ALD thermal desorption of residual elemental As were performed. Photoelectron spectra obtained after ALD of Al2O3 on In0.2Ga0.8As prepared by this method revealed that the interface was free of In, Ga, and As oxides. The resultant metal-oxide-semiconductor capacitors with Pt electrodes exhibited capacitance-derived equivalent oxide thicknesses as small as 1.8nm.

Methodology for Flatband Voltage Measurement in Fully Depleted Floating-Body FinFETs

Among the novel methods for flatband voltage (Vfb) measurement, we demonstrate that a gate-leakage-based technique is the most suitable for measuring Vfb in floating-body MOSFETs with ultrathin gate dielectrics. Starting from carrier separation experiments on planar MOSFETs, we show the universality of the gate conduction mechanism dependence on band alignment for both n- and p-FETs. We demonstrate that metrics based on the gate leakage (either its valence-band electron-tunneling component or its first-order derivative) reflect this dependence and allow equivalent-oxide-thickness-independent Vfb quantification. This dependence is also valid for high-k and capped gate dielectrics, whereas their gate conduction mechanism is dominated by direct tunneling. To illustrate, we extract gate-leakage-derivative-based metrics and measure Vfb of TaN and TiN gate electrodes in multiple-fin FETs integrated on silicon-on-insulator.

Simultaneous large-scale reliability analysis of ultra-thin MOS gate dielectrics using an automated test system

Abstract. This article presents an automated test system targeting the large-scale analysis of ultra-thin MOS gate dielectric degradation. The system allows for stress tests at elevated temperatures as well as supply voltages and long-term tests of thousands of MOS devices simultaneously. The aim is to build-up large and hence significant statistics about the degradation process as a function of time.

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability (NBTI) and stress-induced leakage current (SILC) both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts: the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al2O3, Y2O3, La2O3, Ta2O5, TiO2, ZrO2 and HfO2. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (Jg−Vg) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO2/Al2O3/HfO2 structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.

Microcontact-Printed Self-Assembled Monolayers as Ultrathin Gate Dielectrics in Organic Thin-Film Transistors and Complementary Circuits

We have developed a manufacturing process for organic thin-film transistors and organic complementary circuits in which a microcontact-printed phosphonic acid self-assembled monolayer is employed first as an etch resist to pattern aluminum gate electrodes by wet etching and then as the gate dielectric of the same device. To our knowledge, this is the first report of a printing process for electronic devices that combines the concepts of direct and indirect printing in the same printing step and for the same material by employing a transferred pattern both as an etch resist (indirect printing) and as a functional material as part of the final device (direct printing). Owing to the small thickness and the high quality of the monolayer gate dielectric, the transistors and circuits operate at a low voltage of 3 V.

Localized breakdown in dielectrics and macroscopic charge transport through the whole gate stack: A comparative study

Au – Hf O 2 – Si O x – Si structures with 4nm HfO2 and 1.5nm SiOx interfacial layer (IL) have been electrically stressed by ballistic electron emission spectroscopy (BEES). The continuous BEES stressing at the same location induced gradual degradations and finally led to breakdowns in the IL. The degradation and breakdown cannot be observed using macroscopic conventional current-voltage (IV) measurements over the same area just before and after the BEES stressing process. The localized degradation and breakdown in the dielectric is masked by the macroscopic gate area. Tunneling calculations can estimate the critical area required for a macroscopic device to be able to measure such microscopic breakdown, a problem that becomes increasingly important for characterizing ultrathin gate dielectrics.

Solution Processed Self-Assembled Monolayer Gate Dielectrics for Low-Voltage Organic Transistors

AbstractLow-voltage organic transistors are sought for implementation in high volume low-power portable electronics of the future. Here we assess the suitability of three phosphonic acid based self-assembling molecules for use as ultra-thin gate dielectrics in low-voltage solution processable organic field-effect transistors. In particular, monolayers of phosphonohexadecanoic acid in metal-monolayer-metal type sandwich devices are shown to exhibit low leakage currents and high geometrical capacitance comparable to previously demonstrated self-assembled monolayer (SAM) type dielectrics but with a higher surface energy. The improved surface energy characteristics enable processing of a wider range of organic semiconductors from solution. Transistors based on a number of solution-processed organic semiconductors with operating voltages below 2 V are also demonstrated.

Electrical and Reliability Characteristics of 12-$\hbox{\rm \AA}$ Oxynitride Gate Dielectrics by Different Processing Treatments

Various ultrathin oxynitride gate dielectrics of similar thickness (~1.2 nm) fabricated by a combination of an in situ steam generated and remote plasma nitridation treatment (RPN), an RPN with rapid thermal NO annealing (RPN-NO), and an RPN with rapid thermal O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing (RPN-O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) are reported in this paper. The RPN-NO gate dielectric films show superior interface properties including relatively high nitrogen concentration near the poly-Si/oxide interface and smooth interfaces, excellent electrical characteristics in terms of lower leakage current, better electron and hole channel mobility, higher drive current, and significantly improved reliability such as stress-induced leakage current, hot carrier injection, and negative bias temperature instability, compared to other gate dielectrics fabricated by different processes.

EOT Measurement of Ultra-Thin Gate Dielectrics using the Tunneling Current Regime

Presented in this work is a measurement method to obtain the Equivalent Oxide Thickness (EOT) using the tunneling current regime for ultra-thin gate dielectrics ranging from 1.5 to 16 nm. With the aid of the I-V characteristic of MOS capacitors in a low electric-field range (5-7 MV/cm), EOT was obtained from the slope of the ln(I/Vox2) versus 1/Vox graph for direct or Fowler-Nordheim tunneling current regimes. The average EOT uniformity was obtained for representative populations of tested MOS capacitors (at least a hundred per wafer) and, comparing with the results obtained from C-V measurements, the method was validated.

Ultrashallow depth profiling using SIMS and ion scattering spectroscopy

AbstractThe accuracy of ultrashallow depth profiling was studied by secondary ion mass spectrometry (SIMS) and high‐resolution Rutherford backscattering spectroscopy (HRBS) to obtain reliable depth profiles of ultrathin gate dielectrics and ultrashallow dopant profiles, and to provide important information for the modeling and process control of advanced complimentary metal‐oxide semiconductor (CMOS) design. An ultrathin Si3N4/SiO2 stacked layer (2.5 nm) and ultrashallow arsenic implantation distributions (3 keV, 1 × 1015 cm−2) were used to explore the accuracy of near‐surface depth profiles measured by low‐energy O2+ and Cs+ bombardment (0.25 and 0.5 keV) at oblique incidence. The SIMS depth profiles were compared with those by HRBS. Comparison between HRBS and SIMS nitrogen profiles in the stacked layer suggested that SIMS depth profiling with O2+ at low energy (0.25 keV) and an impact angle of 78° provides accurate profiles. For the As+‐implanted Si, the HRBS depth profiles clearly showed redistribution in the near‐surface region. In contrast, those by the conventional SIMS measurement using Cs+ primary ions at oblique incidence were distorted at depths less than 5 nm. The distortion resulted from a long transient caused by the native oxide. To reduce the transient behavior and to obtain more accurate depth profiles in the near‐surface region, the use of O2+ primary ions was found to be effective, and 0.25 keV O2+ at normal incidence provided a more reliable result than Cs+ in the near‐surface region. Copyright © 2007 John Wiley &amp; Sons, Ltd.

Bathtub-Shaped Hazard Rate Function for Ultra-thin Gate Dielectrics

The hazard rate function for the time-dependent dielectric breakdown of gate dielectrics is reported in this study. Time-to-breakdown data are simulated from a lifetime distribution that considers the physical nature of the breakdown mechanisms. The bathtub-shaped hazard rate function is observed based on a simulation study. A Bayesian approach is adopted in the statistical analysis in order to include knowledge from past experience.

Electron detrapping characteristics in positive bias temperature stressed n-channel metal-oxide-semiconductor field-effect transistors with ultrathin HfSiON gate dielectrics

Electrons trapped in the HfSiON gate dielectrics of n-channel metal-oxide-semiconductor field-effect transistors induced by positive bias temperature stress start to decay when the stress is interrupted or an opposite (recovery) voltage is applied. The decay begins with a quick detrapping within tens of nanoseconds followed by a slow detrapping. The quick detrapping depends on the recovery voltage and the trapping history, whereas the slow detrapping obeys approximately a logarithmic dependence on time with an almost identical slope before saturation. The observed detrapping behavior can be explained by a spatial and/or energetic distribution of trapped electrons in the HfSiON film. The device degradation under various dynamic stresses is found to be almost independent of frequency ranging from 0.001to1MHz, while it is slightly enhanced at 10MHz, probably due to insufficient recovery at the recovering half cycle.

Dependence of electrical properties of HfSiON gate dielectrics on TaSiN metal electrode thickness

We have studied the effect of tantalum–silicon–nitride (TaSiN) metal electrode thickness on the electrical properties of ultrathin HfSiON gate dielectrics formed by atomic layer deposition (ALD) technology using Hf(N(CH3)(C2H5))4 and SiH(N(CH3)2)3 precursors. The TaSiN/HfSiON gate stacks were intended for use in conventional metal gate transistors with a high temperature thermal budget of 950 °C. Leakage current, effective mobility and the drain current in 30 nm thick TaSiN gate electrodes were improved with respect to the values for 10 nm thick TaSiN gate electrodes. From back-side secondary ion mass spectrometry (SIMS) analyses, it was concluded that thick TaSiN gate electrodes suppressed the nitrogen diffusion from the SiN hard mask into HfSiON/SiON gate stacks during activation annealing.