TFET Research Articles

Electrically Doped PNPN Tunnel Field-Effect Transistor Using Dual-Material Polarity Gate with Improved DC and Analog/RF Performance.

A new structure for PNPN tunnel field-effect transistors (TFETs) has been designed and simulated in this work. The proposed structure incorporates the polarity bias concept and the gate work function engineering to improve the DC and analog/RF figures of merit. The proposed device consists of a control gate (CG) and a polarity gate (PG), where the PG uses a dual-material gate (DMG) structure and is biased at -0.7 V to induce a P+ region in the source. The PNPN structure introduces a local minimum on the conduction band edge curve at the tunneling junction, which dramatically reduces the tunneling width. Furthermore, we show that incorporating the DMG architecture further enhances the drive current and improves the subthreshold slope (SS) characteristics by introducing an additional electric field peak. The numerical simulation reveals that the electrically doped PNPN TFET using DMG improves the DC and analog/RF performances in comparison to a conventional single-material gate (SMG) device.

Analysis of a novel Si1-xGex/Si heterojunction stacked oxide double-gate tunnel field-effect transistor with asymmetry structure for improved DC and analog/RF performance

In this work, a novel Si1-xGex/Si heterojunction and stacked oxide double-gate tunnel field-effect transistor with asymmetry structure (ASHJSO-DGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the DC and analog/RF performance of silicon-based double-gate tunnel field-effect transistors with asymmetry structure (ASSi-DGTFETs) is also discussed. Compared to ASSi-DGTFETs, ASHJSO-DGTFET maintains lower off/ambipolar-state current and obtains higher on-state current. The simulation results reveal that the on-state current, switching ratio, and minimum SS of the optimal ASHJSO-DGTFET are 5.27 × 10−5 A/μm, 0.64 × 1012, and 12.3 mV/dec, respectively. Moreover, the maximum gds, gm, ƒT and GBW of ASHJSO-DGTFET are 85 μS/μm, 172 μS/μm, 54.5 GHz and 9.8 GHz, respectively. Therefore, the proposed ASHJSO-DGTFET is more suitable for the ultra-low power integrated circuits.

A new approach for ammonia gas sensing using a source pocket dopingless tunnel FET with PANI catalyst

This article presents a new ammonia (NH3) gas sensor designed using a dopingless tunnel field effect transistor with a SiGe source pocket (SP-DLT) and investigates its sensitivity using a polyaniline (PANI) conducting polymer as the gate catalyst. PANI nanofiber has a greater specific surface area and a linked network structure, which increases its sensing performance as a catalyst. Combining an HfO2 gate dielectric and SiGe source pocket improves the drain current. The sensing film is deprotonated when the PANI conducting polymer is exposed to the gas, reducing the film’s resistance. As a result, more electron or proton transfer is possible, ensuring a more substantial interaction between the sensor and the analyte gas. This modulates the electrical characteristics and work function of the TFET. The sensor’s electrical performance is examined in terms of drain current, average subthreshold swing (SS), electric field, band-to-band tunneling rate (BTBT), and energy band diagram for an ammonia gas pressure (AGP) range of 10−12 torr to 10−9 torr. The sensitivity and selectivity of the proposed PANI-SP-DLT sensor in terms of different metrics, including drain current, average SS, current ratio, transconductance, and gain factor, are further investigated. The study is expanded to consider the impact of temperature affectability and the germanium mole fraction on current sensitivity performance. The Silvaco ATLAS device simulator is used for the brief simulation work for the developed gas sensor.

Asymmetric Dual-Gate Junctionless GNR Tunnel FET as a High-Performance Photosensor With an Electrostatically Improved Photosensitivity: A Quantum Simulation Study

Asymmetric Dual-Gate Junctionless GNR Tunnel FET as a High-Performance Photosensor With an Electrostatically Improved Photosensitivity: A Quantum Simulation Study

Improved Switching and Analog/RF Behaviour of SiGe Heterojunction Dielectric Modulated Dual Material Nano Silicon Tunnel FET for Low Power Applications

Improved Switching and Analog/RF Behaviour of SiGe Heterojunction Dielectric Modulated Dual Material Nano Silicon Tunnel FET for Low Power Applications

Investigating the effects of doping gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications

Influence of Gaussian doping in transistor regions, doping gradient step size (σ), interface trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge-Vertical Tunnel FET (VTFET) is explored using Technology Computer-Aided Design. The DC transfer/output characteristics, ION/IOFF ratio, sub-threshold swing(S); and Analog/RF parasitic capacitances (Cgg, Cgs, and Cgd), transconductance (gm), cut-off frequency (ft), Transit time, efficiency, are examined with Doping Gradient in source & drain, σ variance up to 25 nm, and ITC variation from 1010–1012 cm−2 at Al2O3/Ge interface. Further, linearity parameters, such as gm3, VIP2, VIP3, IMD3, IIP3 &CP1-dB are estimated for optimum Ge-VTFET. For reliability analysis, Ge-VTFET is inspected with temperature deviation from 250 K to 375 K. The proposed Ge-VTFET with the doping gradient in drain and σ of 25 nm revealed excellent performance such as low S ∼ 58 mV/dec, high ION/IOFF ratio ∼ 3 × 105, gm ∼ 6.8 µS, ft ∼ 3.96 GHz, and outstanding reliability even under ITC and temperature deviations, proved Ge-VTFET to be an exceptional contender for low-power switching & analog applications.

Analytical modeling and performance assessment of a Si(1-x) Ge(x) pocketed double-gate dopingless tunnel FET biosensor

An analytical model of a dielectric-modulated double-gate Tunnel FET (DM-DG-TFET) biosensor carrying a Si(1-x) Ge(x) pocket is presented in this paper. The model accounts for the dielectric modulation effect on the surface potential and drain current of the designed biosensor device. An insight into the device physics provides an overview of commanding electrostatics and electrical properties associated with the proposed biosensor. The neutral, as well as charged nature of biomolecules, is considered for modeling and simulation data. Furthermore, the sensitivity for both types of biomolecules is analyzed in terms of threshold voltage (Vth) and on-current (Ion). The modeled and simulated results are extensively studied and compared for their scrupulosity. It has been found that the simulated and modeled results are a close match with each other, and the developed model justifies the physics behind the proposed biosensor. This paper also includes the impact of the nature of biomolecules on various parameters such as threshold voltage, sensitivity metrics, etc.

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance

This paper explores Si/SiGe hetero-junction dielectrically modulated area-scaled tunnel FET (DM-ASTFET) for label-free bio-sensing applications. The proposed sensor can detect bioanalytics such as protein, APTES, Choline Oxidase and Uricase. We have also investigated the influence of quantum confinement on the proposed device, and the onset voltage shifted by 0.1–0.3 V, as reported, without affecting the sensitivity mechanism. Sensitivity improvement is observed when the gate oxide length is 20 nm and the cavity length is 50 nm for a given bio-molecule due to the increased cross-section area for tunneling. The impact of epitaxial engineering on the biosensor's performance is also investigated in this work. A physics-based in-depth explanation of steric hindrance on the performance of the proposed sensor is also presented in this work. Finally, the optimum device design improves the sensitivity of ION ∼×103 and Vth ∼×2 times.

Resonant tunneling and quantum interference of a two-spin system in silicon tunnel FETs

We investigated the resonant tunneling of a two-spin system through the double quantum dots in Al–N-implanted silicon tunnel FETs (TFETs) by electrical-transport measurements and Landau–Zener–Stückelberg–Majorana interferometry with and without magnetic fields. Our experimental results revealed the coexistence of spin-conserving and spin-flip tunneling channels in the two-spin system in non-zero magnetic fields. Additionally, we obtained the spin-conserving/spin-flip tunneling rates of the two-spin system through the double quantum dots in the TFET. These findings will improve our understanding of the two-spin system in silicon TFET qubits and may facilitate the coherent control of quantum states through all-electric manipulation.

Simulation of vertical ballistic quantum-barrier field-effect transistor based on undoped AlxGa1–xAs quantum nanowire

A design-topological solution for a tunnel field-effect transistor of a new type is proposed and the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a cylindrical metallic gate based on a cylindrical undoped AlxGa1–xAs quantum nanowire located in an Al2O3 matrix. For a given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor composition varying along the transistor channel is found, at which, unlike a conventional tunnel field-effect transistor, not only the complete suppression of the quantum barrier for electrons by a positive gate voltage is ensured, but also the minimum possible electrical resistance of the transistor channel. The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-mechanical description of the electron transport in its channel, taking into account the non-parabolic nature of the band structure of the semiconductor.

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Investigation of the effects of trap-assisted tunneling and temperature variations on the sensitivity metrics of a tunnel FET biosensor

The study presented in this paper discusses Trap-Assisted Tunneling (TAT) and temperature variation as the subjects of concern regarding the sensitivity metrics of the presented TFET biosensor. In order to have a minimum amount of process-related variability, the concept of a dopingless TFET structure is used in the development of the suggested device. However, considering the possibility of traps in the doped Silicon–Germanium pocket, an investigation has been conducted using a certain set of models during simulation. The analysis of deep and shallow trap states incorporated to assess TAT current prevails that deep trap affects the biosensors' sensitivity by a significant rate. In addition to this, temperature variations also affect the bandgap narrowing owing to changes in the biosensor's sensitivity.

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

While dealing with the nanoscale regime, most devices make sacrifices in terms of performance. So to meet the performance requirements, Electrostatic doped Vertical Nanowire Tunnel Field Effect Transistor (E-VNWTFET) is proposed and analysed in this work. The dimensions of Electrostatic VNWTFET structure are scaled down and then the analog performance parameters transconductance gm, gm2 (2nd order), gm3 (3rd order) and linearity parameters 2nd order Voltage Interception Point VIP2, 3rd order Voltage Interception Point VIP3, 3rd order Input Interception Point IIP3 and 3rd order Intermodulation Distortion IMD3 are analysed. It is observed that electrostatic technique of doping is better than charge plasma (CP) technique; because in CP technique costly metals are required for doping. The analog performance parameters of E-VNWTFET are investigated and using device simulation the demonstrated characteristics are compared with CP-VNWTFET. After simulation, the device exhibits ON current ION of 3.5 μA μm−1 and OFF current IOFF of 6.6 × 10−18 A μm−1; which offers a significant ION/IOFF of 1011. The reported subthreshold swing and Drain-induced barrier lowering DIBL are approx. 9.7 mV/Decade and 37.8 mV/V respectively.

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the scalability of CTFET under critical dimensions (n- to p-TFET separation, nanosheet pitch, and so on), and find that it is highly scalable. The circuit analysis of CTFET-inverter show high-noise margin (NM) and voltage gains compared to the conventional strained-Si GAA-TFETs at the supply range (V D D) from 0.7 ≥ V D D ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. Improved circuit performance, followed by 12.5% and 21.5% improvements in low and high NMs (NML and NMH) are seen in CTFETs compared to conventional TFETs.

Vacuum Tunneling Transistor with Nano Vacuum Chamber for Harsh Environments.

A nano vacuum tube which consists of a vacuum transistor and a nano vacuum chamber was demonstrated. For the device, a vacuum region is an electron transport channel, and a vacuum is a tunneling barrier. Tilted angle evaporation was studied for the formation of the nano level vacuum chamber structure. This vacuum tube was ultraminiaturized with several tens of 10-18 L scale volume and 10-6 Torr of pressure. The device structure made it possible to achieve a high integration density and to sustain the vacuum state in various real operations. In particular, the vacuum transistor performed stably in extreme external environments because the tunneling mechanism showed a wide range of working stability. The vacuum was sustained well by the sealing layer and provided a defect-free tunneling junction. In tests, the high vacuum level was maintained for more than 15 months with high reliability. The Al sealing layer and tube structure can effectively block exposed light such as visible light and UV, enabling the stable operation of the tunneling transistor. In addition, it is estimated that the structure blocks approximately 5 keV of X-ray. The device showed stable operating characteristics in a wide temperature range of 100-390 K. Therefore, the vacuum tube can be used in a wide range of applications involving integrated circuits while resolving the disadvantages of a large volume in old vacuum tubes. Additionally, it can be an important solution for next-generation devices in various fields such as aerospace, artificial intelligence, and THz applications.

Switching and photosensitive analysis of dopingless tunnel field effect transistor based on cladding layer concept

— In this paper, the switching and photo sensing analysis of cladding layer based dopingless Tunnel FET (CDL-TFET) has been examined under visible range of spectrum. Initially, the impact of cladding layer in DL-TFET on electrical parameter is observed by varying the source material and thickness of source region. Furthermore, CDL-TFET is used for photo sensing application under the light state at various wavelength of light incident. The various optical figure of merits (FoMs) like spectral sensitivity (Sn), Signal to noise ratio (SNR), Responsivity (R), and quantum efficiency (η) is extracted to realize the behavior of photosensor. The maximum value of Sn is 48, R of 0.74 (A/Watt), SNR of 68.8 dB, and η of 3 are obtained at λ = 300 nm. Further, impurity trap charge effects are also observed at the interface and bulk of TFET. Finally, a comparison table has been presented to signify the importance of cladding layer based DL-TFET photo sensor with existing literature.

Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications.

Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application * *This work was supported in part by the Ministry of Science and Technology of Taiwan, R.O.C., under Contact MOST109–2221-E-110–018-MY3.

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve the I ON, resulting in a lower subthreshold swing average (S.S avg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that the S.S avg is improved to 21.5 mV dec−1 with an I ON/I OFF ratio of 106 at V D = 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec−1 has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

In this work, an InGaAs/InAlAs dopingless tunnel field-effect transistor is designed and systematically examined through numerical simulations. In line with the charge plasma concept, the proposed device can not only create a p-n-i-n structure without doping to enhance electron tunneling but also effectively overcome issues caused by doping such as random doping fluctuation, high thermal budget, etc. By investigating the effects of the HfO2 length (L H), the source-side channel length (L sc), and the source-drain electrodes structure on the proposed device, it concludes that the best device characteristic can be acquired when L H is located between 110 nm and 128 nm, L sc=4 nm, and double source-drain electrodes are adopted.