Investigating the effects of doping gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications

Abstract

Influence of Gaussian doping in transistor regions, doping gradient step size (σ), interface trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge-Vertical Tunnel FET (VTFET) is explored using Technology Computer-Aided Design. The DC transfer/output characteristics, ION/IOFF ratio, sub-threshold swing(S); and Analog/RF parasitic capacitances (Cgg, Cgs, and Cgd), transconductance (gm), cut-off frequency (ft), Transit time, efficiency, are examined with Doping Gradient in source & drain, σ variance up to 25 nm, and ITC variation from 1010–1012 cm−2 at Al2O3/Ge interface. Further, linearity parameters, such as gm3, VIP2, VIP3, IMD3, IIP3 &CP1-dB are estimated for optimum Ge-VTFET. For reliability analysis, Ge-VTFET is inspected with temperature deviation from 250 K to 375 K. The proposed Ge-VTFET with the doping gradient in drain and σ of 25 nm revealed excellent performance such as low S ∼ 58 mV/dec, high ION/IOFF ratio ∼ 3 × 105, gm ∼ 6.8 µS, ft ∼ 3.96 GHz, and outstanding reliability even under ITC and temperature deviations, proved Ge-VTFET to be an exceptional contender for low-power switching & analog applications.