Trench-gate Metal-oxide-semiconductor Field-effect Transistors Research Articles

Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs), a comparison among the reliability mechanisms between planar-gate and trench-gate SiC power MOSFETs, which have not been comprehensively summarized, is made in this work. The latest studies focusing on the reliability issues of commercial SiC MOSFET products, including the planar-gate device, the double-trench device and the asymmetric trench-gate device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC trench-gate MOSFETs express quite different instability phenomena from the planar-gate ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power MOSFETs, including the avalanche stress, the short-circuit (SC) stress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

Trap Characterization of Trench-Gate SiC MOSFETs Based on Transient Drain Current

The SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface state is one of the main factors that limit the performance and reliability of the SiC metal-oxide-semiconductor field-effect transistor (MOSFET). In this paper, we use a Bayesian deconvolution algorithm to optimize trap feature extraction based on the transient current method and improve the trap extraction accuracy. Using this method, we study the trap capture mechanism in SiC MOSFETs and mainly characterize the trap position, the trap energy level, and the capture time constant. The results obtained show that there are three different types of traps and defects, two of which are SiC interface traps at the gate-source and gate-drain interfaces, with activation energies of 0.089 eV and 0.035 eV, respectively; the third trap type is an oxide trap, and its time constant does not vary with temperature. The characterization results are verified via deep level transient spectroscopy, and the results show reasonable agreement with those obtained by the method proposed in this paper. This method can be combined with electrical stress testing in long-term reliability research to realize nondestructive characterization of the defects of SiC MOSFETs.

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (UMOSFET) with semi-super-junction shielded structure (SS-UMOS) is proposed and compared with conventional trench MOSFET (CT-UMOS) in this work. The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET. In particular, the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed. The on-resistance of SS-UMOS with grounded (G) and ungrounded (NG) p-pillar is reduced by 52% (G) and 71% (NG) compared to CT-UMOS, respectively. Additionally, gate oxide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions. Thus, a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer. However, the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar, resulting in a large electric field of 2.7 MV/cm at the gate oxide layer. Moreover, the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18% compared with CT-UMOS. On the contrary, the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three. The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications, and will provide a valuable idea for device design and circuit applications.

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

A novel SiC double-trench metal-oxide-semiconductor field effect transistor (MOSFET) with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source trench (MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage V F and suppresses the bipolar degradation phenomena. The V F of 1.70 V (@I ds = –100 A/cm2) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET (DT MOS). Meanwhile, the reverse recovery charge Q rr of the MT MOS is 58.7% lower than that of the DT MOS at I load = 700 A/cm2, and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches, the MT MOS preserves the same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on breakdown voltage and R ON,sp compared to the trench gate MOSFET with planar integrated SBD (ST MOS).

Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example.

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

Analysis of Electrical Characteristics in 4H-SiC Trench-Gate MOSFETs with Grounded Bottom Protection p-Well Using Analytical Modeling

A new analytical model to analyze and optimize the electrical characteristics of 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors (TMOSFETs) with a grounded bottom protection p-well (BPW) was proposed. The optimal BPW doping concentration (NBPW) was extracted by analytical modeling and a numerical technology computer-aided design (TCAD) simulation, in order to analyze the breakdown mechanisms for SiC TMOSFETs using BPW, while considering the electric field distribution at the edge of the trench gate. Our results showed that the optimal NBPW obtained by analytical modeling was almost identical to the simulation results. In addition, the reverse transfer capacitance (Cgd) values obtained from the analytical model correspond with the results of the TCAD simulation by approximately 86%; therefore, this model can predict the switching characteristics of the effect BPW regions.

Formation of highly vertical trenches with rounded corners via inductively coupled plasma reactive ion etching for vertical GaN power devices

A trench-gate metal-oxide-semiconductor field-effect transistor (T-MOSFET) has great potential for use in gallium nitride (GaN)-based vertical power switching devices owing to its high blocking voltage and high current capability. To form an optimal trench shape that has highly vertical sidewalls and rounded corners, we developed a dry-etching technique using inductively coupled plasma reactive ion etching (ICP-RIE). A highly vertical trench was obtained by including SiCl4 reactive gas mixed with Cl2 gas in the ICP-RIE process, where Si-related byproducts suppressed the etching of the sidewall and allowed selective etching in the vertical direction. We found that the optimization of the bias power was a key to suppress the formation of subtrenches and to avoid an isotropic etching mode. The optimal etching condition leads to natural formation of rounded corners at the trench bottom. In addition, a multistep-bias etching technique was applied to reduce etching-induced damage. Cross-sectional transmission electron microscopy images revealed that lattice distortion on the sidewall surface was eliminated by multistep-bias etching. Based on the rectification properties of the Schottky barrier diodes formed on the trench sidewalls, the Schottky barrier height was comparable to the not-etched surfaces. This indicates that the gap states caused by etching-induced damage can almost be eliminated in the multistep-bias process. The proposed technique is suitable for GaN-based vertical T-MOSFETs.

Improved 4H-SiC UMOSFET with super-junction shield region* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045), the Youth Foundation of the Education Department of Jiangxi Province, China (Grant No. GJJ191154), and the Youth Foundation of Ping Xiang University, China (Grant No. 2018D0230).

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance (R on,sp). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field (E-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R on,sp of the modified structure, and breakdown voltage (V BR) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit () is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge (Q gd) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V BR of the device without degradation of dynamic performance.

Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications

This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron velocity, threshold voltage (V th), electron mobility, and sub-threshold swing (SS) of these devices has been performed. Results reveal a 43.85% improvement in SS and 9.83% decrement in V th for GaN-BTG-MOSFET. Furthermore, the frequency analysis has been performed in terms of scattering (S) parameters, cut-off frequency (f T) and maximum oscillator frequency (f MAX) to show how the device is also suitable for radio frequency applications. Furthermore, the study of parametric variation of GaN-BTG-MOSFET with the change in channel length, oxide thickness (t ox), and doping concentration has also been presented. Results show that GaN-BTG-MOSFET can act as a promising structure for further scaling down of the trenched MOSFET and assures better performance for sub-20 nm trenched MOSFET.

Fast Switching $\beta$ -Ga2O3Power MOSFET With a Trench-Gate Structure

In this letter, trench-gate metal–oxide–semiconductor field-effect transistors on (010) $\beta $ -Ga2O3 epitaxial layer are fabricated. Enhancement mode is achieved by the gate-recess process, through thoroughly depleting the $\beta $ -Ga2O3 channel to get a positive threshold voltage. For the first time, by using a dynamic parameter test system, the Ga2O3 MOSFET with 2- $\mu \text{m}$ gate length is characterized to present short switching time, including turn-on time ( $\textit {t}_{ \mathrm{\scriptscriptstyle ON}}$ ) of 28.6 ns and turn-off time ( $\textit {t}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of 94.0 ns. In addition, OFF-state interelectrode parasitic capacitances, including input capacitance ( $\textit {C}_{\text {iss}}$ ) of 37 pF/mm, output capacitance ( $\textit {C}_{\text {oss}}$ ) of 42 pF/mm, and reverse transfer capacitance ( $\textit {C}_{\text {rss}}$ ) of 14 pF/mm are also obtained, which can account for the high switching speed. The static and dynamic switching properties of the trench-gate device show the potential of $\beta $ -Ga2O3 MOSFET for the high-speed switching applications.

Comprehensive Characterization of the 4H-SiC Planar and Trench Gate MOSFETs From Cryogenic to High Temperature

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance ( ${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$ ) and threshold voltage ( ${V}_{\text {th}}$ ) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times ( ${T}_{r}$ and ${T}_{f}$ ) and the corresponding energy loss ( ${E}_{r}$ and ${E}_{f}$ ) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures.

3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field

A critical issue for SiC trench gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) is gate oxide shielding from the electric field at the trench bottom. In this letter, low ON-resistance with low gate electric field was achieved in a 3.3-kV-class UMOSFET with a unique hexagonal buried p-base region formed by MeV ion implantation. The shielding effect was further enhanced by a self-aligned trench bottom shielding region. The specific ON-resistance, with and without the trench bottom shielding region, was 8.3 and 9.4 $\text {m}\Omega \text {cm}^{2}$ , respectively. The blocking voltage in each case was $\sim 3800$ V. The electric field in the gate oxide with the trench bottom shielding region was reduced to 2.5 MV/cm at 3300 V.

Power trench gate MOSFET with an integrated 6-pack configuration for a 3-phase inverter

In this paper, we present a new 6-pack power module for a 3-phase inverter that is integrated with the six trench gate double diffused metal-oxide semiconductor field-effect transistor (TDMOS) on a single chip. An integration of each power device is performed through a trench isolation technique using deep reactive-ion etching trench technologies. Through this new technology, the integrated power metal-oxide semiconductor field-effect transistor (MOSFET) produces a high current of above 30 A at a gate bias of 10 V. In addition, each trench power MOSFET (1-pack) has a minimum specific on-resistance of 21 mohm.cm2 and a typical breakdown voltage of 95 V. The trench isolation provides good isolation up to 120 V. The measurement results show that this 6-pack structure can successfully be integrated with other analog/driver integrated circuit on a single chip. Furthermore, to monitor the operating current of the MOSFET under an inverter-operating condition, sensing FET is integrated a FET into the main MOSFET source region without compromising either the area or the operation of the MOSFET.

Integratable trench MOSFET with ultra‐low specific on‐resistance

A novel integratable metal–oxide–semiconductor field-effect transistor (MOSFET) with a trench source (TS) and a trench gate (TG) (TS–TG MOSFET) is proposed. The TS and TG cause a strong assistant depletion effect and thus dramatically increase the N-drift doping concentration (N d). Moreover, an accumulation layer beside the TG is formed and offers a continuous low-resistance path in the on-state. Therefore, the novel MOSFET effectively reduces specific on-resistance (R on,sp). The TS–TG MOSFET not only has the merits of low R on,sp and the easy parallel connection of vertical double-diffused MOS, but also possesses the advantage of ease of integration like the LDMOS. The breakdown voltage (BV) of 61 V and the R on,sp of 0.133 mΩ cm2 are obtained for the TS–TG MOSFET, with a significant optimised trade-off between R on,sp and BV.

A novel trench gate MOSFET with a multiple-layered gate oxide for high-reliability operation

Gate dielectrics in trench structures for trench gate metal oxide semiconductor field-effect transistor (MOSFET) power devices are very important to realize excellent characteristics. In this paper we describe multiple-layer gate dielectrics for trench gate MOSFETs with both thermal and chemical vapor deposition (CVD) gate oxides that exhibit excellent gate oxide properties and surface roughness. Through various trench etching experiments for better surface conditions in the trench, the optimum etching gas chemistry and etch conditions were found. The destruction of gate dielectric in trench gate MOSFET occurs at the top and the bottom trench corner edges. The structure of the gate electrode is pulled out with the polysilicon layer which is buried in the trench. Thus, high electric field operation is inevitable at the gate between source diffusion and the gate polysilicon. Moreover, the trench corner oxide suffers from the high electric field. We propose a multiple-gate dielectric structure of a thermal oxide and CVD oxide for highly reliable operation of the device. This enables trench surface smoothing and low thermal stress at the trench corners and provides the oxide thickness uniformity, giving superior device characteristics of high breakdown voltage and low leakage current. These improvements are caused by the excellent quality of the gate oxide and the good thickness uniformity that is formed at the inner trench with a specific geometrical factor.

Improvement of floating island and thick bottom oxide trench gate metal–oxide–semiconductor field-effect transistor

A metal–oxide–semiconductor field-effect transistor (MOSFET) structure called FITMOS (floating island and thick bottom oxide trench gate MOSFET) has been successfully developed that exhibits outstanding low loss. This unique feature of the FITMOS is realised by fabricating deep trenches in the n-type drift layer, by forming p-type floating islands below the individual trenches using self-aligned ion implantation, and by fabricating trench gates with a thick oxide layer on the bottom. Then, the trade-off between the drain-to-source breakdown voltage and on-resistance has been further optimised by changing the shape of the floating islands from spherical to ellipsoidal. By improving the device structure, a breakdown voltage of 91 V and specific on-resistance of 41.5 mΩ mm2 have been obtained in a 4.5×4.5 mm square device with ellipsoidal floating islands. The relationship between the device structure and the reverse recovery characteristics is also investigated.

Power metal oxide semiconductor field effect transistors with accurate current sensing function over a wide temperature range

In the power metal oxide semiconductor field effect transistor (MOSFETs) with a current-sensing function (current-sensing power MOSFETs), temperature dependence in the current sense ratio has been a significant problem. The authors discuss the mechanisms involved in these temperature-dependent current sense ratios by investigating the following factors: (i) drift layer impurity concentration and layer thickness and (ii) chip size and the position of the sense MOSFET part in the chip. Furthermore, it is shown that temperature dependence in the sense ratio can be reduced by adopting a floating island and thick bottom oxide trench gate MOSFET (FITMOS) structure or by arranging the sense MOSFET part at the centre of the chip.

A method for generating structurally aligned grids for semiconductor device simulation

The quality of the numeric approximation of the partial differential equations governing carrier transport in semiconductor devices depends particularly on the grid. The method of choice is to use structurally aligned grids since the regions and directions therein that determine device behavior are usually straightforward to find as they depend on the distribution of doping. Here, the authors present an algorithm for generating structurally aligned grids including anisotropy with resolutions varying over several orders of magnitude. The algorithm is based on a level set approach and permits to define the refined resolutions in a flexible manner as a function of doping. Furthermore, criteria on grid quality can be enforced. In order to show the practicability of this method, the authors study the examples of a trench gate metal-oxide-semiconductor field-effect transistor (TMOSFET) and a radio frequency silicon-on-insulator lateral double diffused metal-oxide-semiconductor (RF SOI LDMOS) power device using the device simulator MINIMOS NT, where simulations are performed on a grid generated by the new algorithm. In order to resolve the interesting regions of the TMOSFET and the RF SOI LDMOS power device accurately, several regions of refinement were defined where the grid was grown with varying resolutions.