Formation of highly vertical trenches with rounded corners via inductively coupled plasma reactive ion etching for vertical GaN power devices

Abstract

A trench-gate metal-oxide-semiconductor field-effect transistor (T-MOSFET) has great potential for use in gallium nitride (GaN)-based vertical power switching devices owing to its high blocking voltage and high current capability. To form an optimal trench shape that has highly vertical sidewalls and rounded corners, we developed a dry-etching technique using inductively coupled plasma reactive ion etching (ICP-RIE). A highly vertical trench was obtained by including SiCl4 reactive gas mixed with Cl2 gas in the ICP-RIE process, where Si-related byproducts suppressed the etching of the sidewall and allowed selective etching in the vertical direction. We found that the optimization of the bias power was a key to suppress the formation of subtrenches and to avoid an isotropic etching mode. The optimal etching condition leads to natural formation of rounded corners at the trench bottom. In addition, a multistep-bias etching technique was applied to reduce etching-induced damage. Cross-sectional transmission electron microscopy images revealed that lattice distortion on the sidewall surface was eliminated by multistep-bias etching. Based on the rectification properties of the Schottky barrier diodes formed on the trench sidewalls, the Schottky barrier height was comparable to the not-etched surfaces. This indicates that the gap states caused by etching-induced damage can almost be eliminated in the multistep-bias process. The proposed technique is suitable for GaN-based vertical T-MOSFETs.