Transistor Channel Length Research Articles

Self-aligned flexible organic thin-film transistors with gates patterned by nano-imprint lithography

Many applications that rely on organic electronic circuits still suffer from the limited switching speed of their basic elements – the organic thin film transistor (OTFT). For a given set of materials the OTFT speed scales inversely with the square of the channel length, the parasitic gate overlap capacitance, and the contact resistance. For maximising speed we pattern transistor channels with lengths from 10μm down to the sub-micrometre regime by industrially scalable UV-nanoimprint lithography. The reduction of the overlap capacitance is achieved by minimising the source–drain to gate overlap lengths to values as low as 0.2μm by self-aligned electrode definition using substrate reverse side exposure. Pentacene based organic thin film transistors with an exceptionally low line edge roughness <20nm of the channels, a mobility of 0.1cm2/Vs, and an on–off ratio of 104, are fabricated on 4″×4″ flexible substrates in a carrier-free process scheme. The stability and spatial distribution of the transistor channel lengths are assessed in detail with standard deviations of L ranging from 185 to 28nm. Such high-performing self-aligned organic thin film transistors enabled a ring-oscillator circuit with an average stage delay below 4μs at an operation voltage of 7.5V.

&lt;b&gt;Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC) by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ)-comparator, the encoder and the parallel input serial output (PISO) register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm 2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

Low-voltage pentacene photodetector based on a vertical transistor configuration

Due to the excellent characteristics of field-effect transistor and its high absorption coefficient in the visible region, pentacene has been widely used in phototransistors. The channel length of the vertical transistor could be designed to be very short (on the order of nanometers). In this way, the device performances and its working frequency can be effectively improved, and the energy consumption can be reduced simultaneously. In this paper, we fabricate a kind of low-voltage pentacene photodetector ITO(S)/Pentacene/Al(G)/Pentacene/Au(D), based on the vertical transistor configuration. The threshold voltage and “on/off” current ratio are -0.9 V and 104 at a low working-voltage of -3 V, respectively. The pentacene photodetector ITO/Pentacene(80 nm)/Al(15 nm)/Pentacene (80 nm)/Au exhibits a good p-type transistor behavior and low-voltage-controlling performance. The photosensitivity and responsivity vary with incident monochromatic light from 350 nm to 750 nm, and the photosensitivity peak of 308 is obtained at 350 nm with a responsivity of 219 mA·W-1, which is even higher than that of the standard Si-based photodetector under 350 nm incident light. Therefore, this work provides an easy way to fabricate a high sensitivity all-organic photodetector working at low voltages.

Short-channel effect and device design of extremely scaled tunnel field-effect transistors

For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of tunnel-field effect transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5×1017cm−3 and a minimum length of 20nm enables 5nm TFETs to exhibit favorable on–off switching characteristics. In sub-20nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25nm to sustain reversely biased drain voltage of 0.7V. The asymmetric Si1−xGex source heterojunction is combined with the minimum drain design in 5nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5nm TFETs.

X‐band CMOS power amplifier with high efficiency for motion detection radar

ABSTRACTThis article describes a highly efficient X‐band CMOS power amplifier. To obtain high drain voltage for high power, instead of using the typical cascode structure, we use a common‐source structure with a long channel length transistor. Generally, to enable high operating speed at high frequency, smaller transistor technology is used, but we demonstrate that using large transistor technology is also possible. The proposed power amplifier is designed with transistors of 300‐nm channel length in a common‐source structure using a differential structure of RFCMOS technology. Consequently, the maximum output power is 19 dBm with a power added efficiency of 40.5% at an input power of 5 dBm. This RFCMOS power amplifier includes all matching circuits and biasing circuits, and no external components are required. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2552–2557, 2014

An Improved A Low Power CMOS TIQ Comparator Flash ADC

This paper was presented the design of a threshold inverter quantized (TIQ) comparator in flash analog to digital converter. The TIQ-comparator has a high speed response; however this circuit involves a lot of transistors hence wasteful power consumption. The design is intended to obtain a low-power TIQ-comparator and reduces the area of the chip in 0.18 µm CMOS technology. The method was proposed to set each of the transistor channel length for the threshold voltage difference gained of the inverter each in the TIQ-comparator and adding a transistor as compensation to overcome the limitations of the length channel expansion due to the body effect influence. This method has reduced the drain current of CMOS transistors; hence the power dissipation can be reduced. The event has achieved low power dissipation of 31.14 µW and a chip size of 1065 µm2 with 0 to 0.6 V input signal condition.

Empirical Data of the Metal-Ferroelectric-Semiconductor Field Effect Transistor Polarization and Channel Resistance for Timing and Retention Analysis

In this paper, empirical data describing the channel resistance and polarization of several metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) is presented. Various channel length and width transistors were used to describe the channel resistance under various biasing conditions and in both positive and negative polarization states. The presented results and analysis provide insight into the switching speed between polarization states as well as the timing and retention constraints for a given set of device dimensions. This is of particular value when considering circuit designs that utilize MFSFETs, especially digital memory circuits.

General Strategy for Self-Assembly of Highly Oriented Nanocrystalline Semiconducting Polymers with High Mobility

Solution processable semiconducting polymers with excellent film forming capacity and mechanical flexibility are considered among the most progressive alternatives to conventional inorganic semiconductors. However, the random packing of polymer chains and the disorder of the polymer matrix typically result in low charge transport mobilities (10(-5)-10(-2) cm(2) V(-1) s(-1)). These low mobilities compromise their performance and development. Here, we present a strategy, by utilizing capillary action, to mediate polymer chain self-assembly and unidirectional alignment on nanogrooved substrates. We designed a sandwich tunnel system separated by functionalized glass spacers to induce capillary action for controlling the polymer nanostructure, crystallinity, and charge transport. Using capillary action, we demonstrate saturation mobilities with average values of 21.3 and 18.5 cm(2) V(-1)s(-1) on two different semiconducting polymers at a transistor channel length of 80 μm. These values are limited by the source-drain contact resistance, Rc. Using a longer channel length of 140 μm where the contact resistance is less important, we measured μh = 36.3 cm(2) v(-1) s(-1). Extrapolating to infinite channel length where Rc is unimportant, the intrinsic mobility for poly[4-(4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b']dithiophen-2-yl)-alt-[1,2,5]thiadiazolo[3,4-c]pyridine] (Mn = 140 kDa) at this degree of chain alignment and structural order is μh ≈ 47 cm(2)v(-1) s(-1). Our results create a promising pathway toward high performance, solution processable, and low-cost organic electronics.

Optimization and Simulation of humidity sensor readout circuitry using two stage op amp

In this paper a humidity sensor readout circuitry using two stage opamp is designed. This circuitry is realized in TSMC 0.18μm CMOS Technology. Designing of two-stage op-amps is a multi-dimensional- optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP circuit is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin and CMRR 39dB, Slew Rate 154dB, UGB (Unity Gain Bandwidth) are in a higher unity gain frequency under the same load condition. Also presented humidity sensor can achieve good linearity over the relative humidity range from 20% to 80%. The total power dissipation of readout circuitry is 21.8 pW. Terms: CMOS humidity sensor, humidity sensor, Op-Amp. I. Introduction Humidity sensors have a widely used in application areas, including agriculture, climate control, food storage, and domestic appliances. In order to satisfy the requirements of these applications, humidity sensors should provide high sensitivity over a wide range of humidity and temperature and linear response. Other important parameters of the humidity sensors can be listed as long-term stability, response time, and power consumption. A desirable feature of the humidity sensors is their compatibility with standard IC fabrication technologies. There are various types of humidity sensors based on the sensing principle they use, such as resistive, mechanical, gravimetric, capacitive, and thermal humidity sensors. This approach provides a number of advantages. The diodes can be heated up with a low power, and they provide high sensitivity. As the diodes are heated up, no water condensation can occur on the sensing elements. In most of the electronics circuits the Operational Amplifiers is the most common building blocks. So as the transistor channel length and power supply is reduced then the design of Op amps face continuous challenge. Due to different aspect ratio (W/L), there is a tradeoff among speed, gain, power and the other parameters. The implementation of a CMOS OPAMPs that combines a considerable dc gain with higher unity gain frequency has been a most difficult problem. There has been several circuits design to evaluate this problem. The purpose of the design methodology in this paper is to design accurate equations for the design of high- gain 2 staged CMOS op-amp. Outline of paper

Timing optimization of a H-tree based digital silicon photomultiplier

This paper presents a compresensive analysis of timing resolution for a digital silicon photomultiplier (D-SiPM) using a SPICE simulator. Generally, digital silicon photomultipliers (D-SiPMs) have a full-width-half-maximum (FWHM) single-photon timing resolution (SPTR) of more than 100 ps, often of several hundreds picoseconds. This is primarily due to detector jitter, circuit noise, and routing skew. Circuit noise and skew, in turn, strongly depend on the SiPM design; this dependency has been investigated by varying transistor size and transistor channel length, wire resistance, and capacitance. The scalability of the method has been validated by considering D-SiPMs of different sizes and with a variety of signal distribution architectures.

(Invited) Nanoscale Heterogeneous Reactions and Interfaces in Ge/Si and for III-V on Si Integrated Devices

In the pursuit of realizing sub-10 nm transistor channel lengths in homogenous and heterostructured materials, nanoscale defects and hetero-interfaces can significantly impact the formation of alloyed metal contacts conventionally used in CMOS devices. We utilize in-situ transmission electron microscopy to unveil new observations on the detailed formation of such alloys and interfaces at an atomic scale by capturing single nucleation events during the reaction of Ni with Si, Ge and Ge/Si core/shell nanowires and assess their resultant transistor performance. We then utilized the NiSi reaction to develop a novel heterogeneous integration process for III-V semiconductors on planar and patterned Ni electrodes in a fab-compatible process. We demonstrate the operation of the first InGaAs FinFETs on Si.

(Invited) Fundamentals in MoS2 Transistors: Dielectric, Scaling and Metal Contacts

The rise of two-dimensional (2D) crystals has given new challenges and opportunities to the device research. The semiconducting MoS2 has been considered as a promising ultrathin body channel for future microelectronic and optoelectronic devices. In this paper, we focus on the fundamental device properties in MoS2 transistors. In the first part we introduce the dielectric integration on MoS2 and other 2D crystals by atomic layer deposition, revealing the similarities and differences of dielectric integration on bulk and 2D crystals. Then we discuss scaling of channel length and width of MoS2 transistors. We also present the different metal contacts on MoS2, showing Fermi level pinning at metal/2D interfaces. Finally we demonstrate a statistical study on CVD based single layer MoS2 transistors, therefore to show potentials and limitations on these 2D crystals in device applications.

Coupled Electro–Thermal Simulation for Self-Heating Effects in Graphene Transistors

The effects of self-heating on graphene transistor characteristics are examined by self-consistently solving the coupled nonequilibrium Green's function transport equation with the thermal transport equation. The results indicate that the substrate and gate insulator have significant effects on the temperature rise, decrease of on-current, and lowering of transconductance through surface polar phonon scattering, which causes self-heating effects. For graphene transistors with the channel length of a few hundred nanometers, the temperature rise of about 110 K and on-current lowering of about 17% are predicted because of self-heating. This indicates the importance of a coupled electro-thermal simulation for predicting graphene device characteristics and of thermal engineering on device performance. The dependence of the self-heating effects on the transistor channel length and phonon energy are also examined.

A propagation concept of negative bias temperature instability along the channel length in p-type metal oxide field effect transistor

Combining simultaneously on the fly interface-trap (OTFIT) and the reverse voltage variation of source and drain (S/D) during measurement phase of measure/stress/measure (MSM) sequences, we have been able to scan the negative bias temperature instability (NBTI) across the channel length of PMOS transistors. In addition, we have analyzed the generation and evolution of interface-trap distribution with respect to the transistor gate length. We have found that NBTI-induced interface-trap density, ΔNit are not uniform along the channel. The experimental results reveal an evident propagation of the NBTI degradation. This propagation starts from S/D channel edges and penetrates into the channel center. It is accelerated by temperature and electric field until saturation. However, field-accelerated propagation seems more important than temperature-accelerated one. Further, transistors with shorter channel length degrade more rapidly than those with longer channel length. We have also shown that the channel length has a great effect on NBTI features such as the apparent activation energy and time power-law exponent. These results suggest that diffusion-limited process is not the sole source of the time degradation dependence, but also gate length have to be taken into account.

Aerosol Jet Printed, Low Voltage, Electrolyte Gated Carbon Nanotube Ring Oscillators with Sub-5 μs Stage Delays

A central challenge for printed electronics is to achieve high operating frequencies (short transistor switching times) at low supply biases compatible with thin film batteries. In this report, we demonstrate partially printed five-stage ring oscillators with >20 kHz operating frequencies and stage delays <5 μs at supply voltages below 3 V. The fastest ring oscillator achieved 1.2 μs delay time at 2 V supply. The inverter stages in these ring oscillators were based on ambipolar thin film transistors (TFTs) employing semiconducting, single-walled carbon nanotube (CNT) networks and a high capacitance (∼1 μF/cm(2)) ion gel electrolyte as the gate dielectric. All materials except the source and drain electrodes were aerosol jet printed. The TFTs exhibited high electron and hole mobilities (∼20 cm(2)/(V s)) and ON/OFF current ratios (up to 10(5)). Inverter switching times t were systematically characterized as a function of transistor channel length and ionic conductivity of the gel dielectric, demonstrating that both the semiconductor and the ion gel play a role in switching speed. Quantitative scaling analysis suggests that with suitable optimization low voltage, printed ion gel gated CNT inverters could operate at frequencies on the order of 1 MHz.

Design of Low Voltage, Low Power (IF) Amplifier Based-On MOSFET Darlington Configuration

This paper presents a different approach of Intermediate Frequency (IF) amplifier using 0.18 μm MIETEC technology channel length of MOSFET Darlington transistors. In contrast to Bipolar conventional Darlingtonpair, a MOSFET Darlington configuration is employed to reduce supply voltage (VDD) and DC consumption power (Pc). The frequency response parameters of the proposed design such as bandwidth, gain bandwidth product, input/output noises and noise figure (NF) are improved in proposed (IF) amplifier. Moreover, a dual-input and dual-output (DIDO) IF amplifier constructed from two symmetrical single input and single output (SISO) (IF) amplifier is proposed too. The idea is to achieve improved bandwidth, and flat response, because these parameters are very important in high frequency applications. Simulation results that obtained by P-SPICE program are 1.2 GHz Bandwidth (BW), 3.4 GHz (gain bandwidth product), 0.5 mW DC consumption power (Pc) and the low total output noise is 12 nV with 1.2 V single supply voltage.

An Integrated ISFET pH Microsensor on a CMOS Standard Process

We present the design and integration of a nine-pH microsensor array on a single silicon substrate with its own signal readout circuit, integrated in a 0.6-μm commercial standard complementary metal oxide semiconductor (CMOS) process. An ion sensitive field effect transistor (ISFET) has been used as pH microsensor and an instrumentation amplifier as the read-out circuit. The ISFET structure is conformed by the channel length and ratio of MOS transistor, gate extended and the selective membrane, for which silicon nitride (Si3N4) is employed as an ion selective element. The complete design includes shielding around the pH microsensor and the readout circuit to avoid leakage of current to the substrate. The readout circuit is composed by three operational amplifiers and resistances that form the instrumentation amplifier, with a ±2.5 V bias has a 50 dB gain, power supply rejection ratio (PSSR) of 120 dB and common mode rejection ratio (CMRR) of 127 dB. The complete system is integrated in a 1.12 mm2 silicon area; it presents a 59 mV/pH linearity, within a concentration range of 2 to 12 of pH level, making it a good alternative for biological or medical applications.

N‐Type Self‐Assembled Monolayer Field‐Effect Transistors and Complementary Inverters

AbstractThis work describes n‐type self‐assembled monolayer field‐effect transistors (SAMFETs) based on a perylene derivative which is covalently fixed to an aluminum oxide dielectric via a phosphonic acid linker. N‐type SAMFETs spontaneously formed by a single layer of active molecules are demonstrated for transistor channel length up to 100 μm. Highly reproducible transistors with electron mobilities of 1.5 × 10−3 cm2 V−1 s−1 and on/off current ratios up to 105 are obtained. By implementing n‐type and p‐type transistors in one device, a complimentary inverter based solely on SAMFETs is demonstrated for the first time.

Ultrashort Channel Silicon Nanowire Transistors with Nickel Silicide Source/Drain Contacts

We demonstrate the shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) by a controlled reaction with Ni leads on an in situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 °C. NiSi(2) is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (μA/μm) and a maximum transconductance of 430 (μS/μm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of 17 nm to 3.6 μm. Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs, and that limits transport parameter extraction from SB-FETs using conventional field-effect transconductance measurements.

안티퓨즈 MOS capacitor를 이용한 OTP 소자의 프로그래밍 후의 저항특성

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.