Transistor Channel Length Research Articles

Electronic Transport Properties of Ensembles of Perylene‐Substituted Poly‐isocyanopeptide Arrays

AbstractThe electronic transport properties of stacks of perylene‐bis(dicarboximide) (PDI) chromophores, covalently fixed to the side arms of rigid, helical polyisocyanopeptides, are studied using thin‐film transistors. In device architectures where the transistor channel lengths are somewhat greater than the average polymer chain length, carrier mobilities of order 10−3 cm2 V−1 s−1 at 350 K are found, which are limited by inter‐chain transport processes. The influence of π–π interactions on the material properties is studied by using PDIs with and without bulky substituents in the bay area. In order to attain a deeper understanding of both the electronic and the electronic‐transport properties of these systems, studies of self‐assembly on surfaces are combined with electronic characterization using Kelvin probe force microscopy, and also a theoretical study of electronic coupling. The use of a rigid polymer backbone as a scaffold to achieve a full control over the position and orientation of functional groups is of general applicability and interest in the design of building blocks for technologically important functional materials, as well as in more fundamental studies of chromophoric interactions.

Sensitivity of static noise margins to random dopant variations in 6-T SRAM cells

The random dopant induced fluctuations of static noise margins (SNM) in 6-T SRAM cells are analyzed by using the formalism of doping sensitivity functions, which show how sensitive the SNM are to variations of the doping concentration at different locations inside the cell. The technique presented in this article is based on a full circuit perturbation theory at the level of each device transport model. It provides important information for the design and optimization of SNM and can capture correlation effects of doping fluctuations inside the same semiconductor device and between more devices. The bias points and the magnitude of random dopant induced fluctuations are computed by solving the Poisson, current continuity, and density–gradient equations for all the devices self-consistently (mixed-mode simulation). Simulation results for a well scaled SRAM cell with 30 nm channel length transistors show that the most sensitive regions to doping fluctuations extend for approximately 10 nm below the oxide/semiconductor interface and are located in the middle of the conduction channels for both the p-channel and n-channel transistors. It is apparent that random dopant induced fluctuations can significantly impinge on the yield and reliability of SRAM circuits and constitute a fundamental limit for further scaling unless these devices are properly optimized.

P‐79: Characterization of Narrow‐Channel TFT Using Asymmetric Halftone Exposure

AbstractAsymmetric slits were designed to make channel length (L) of thin film transistor (TFT) narrower. Amorphous silicon TFTs, having various channel lengths in the range of 1.5μm to 4μm, were successfully fabricated by optimizing two different slit widths beyond its own resolution limitation of a exposure system. Also, characteristics of TFTs having channel length below 4μm were investigated in this paper.

Solution-based hybrid printing process for tiny channel length of organic transistors

Inkjet printing technique has been studying intensively on organic electronics, but its resolution is limited to about 20 to 50 μm due to the nozzle size and the interaction between the ink and substrates. In order to reduce the patterning feature of IJP, we use the contact printing as an auxiliary process to pre-define the desired deposition pattern. By use of the wetting and the dewetting surface properties, the inkjet printed ink will self-align to the wetting surface to afford tiny feature. In this paper, Poly[3,4-(ethylenedioxy)thiophene] (PEDOT) was selected and patterned as electrodes of organic transistors. Octadecyltrichlorosilane (OTS) thin layer was used as the surface modifier. The minimum channel length can achieve to about 5 μm or so. The field-effect mobility of 0.001 cm2/V-s and on/off current ratios of 103 were obtained in the ploy(3-hexylthiophene) organic thin film transistors fabricated by this proposed process.

Micrometer-scaled Channel Lengths of Organic Field-effect Transistors Patterned by Using PEDOT/PSS Microfibers

Abstract We have easily fabricated channel patterns of organic field-effect transistors (OFET), in which channel lengths were ca. 5 μm, by using wet-spun poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate) (PEDOT/PSS) microfibers with diameters of ca. 5 μm. Pentacene-based OFETs with a bottom-contacted configuration, fabricated on the channel patterns, showed a hole mobility of 10−3 cm2 V−1 s−1 simply reflecting FET characteristics of the pentacene, and showed large current of 8 μA (VDS=−50 V; VG=−50 V) reflecting shorter channel length of the devices.

Emerging Research Nanoelectronic Devices: The Choice of Information Carrier

Many different approaches are being explored for information carriers that will enable continued geometrical scaling beyond the estimated physical limits of electron-based devices. In this paper we offer the proposition that as transistor channel length decreases below 5 nm, the mass of the information carrier must rapidly increase if acceptable ON-OFF switch characteristics are to be maintained. Several different possibilities for the realization of sub-5-nm switches are outlined.

Non-percolating nanotube networks for thin film transistors: A pathway to channel length reduction

This study outlines a method to increase the transconductance of thin film transistors (TFTs) by assembling non-percolating random arrays of carbon nanotubes. It represents an effective, simple tool to substantially reduce the transistor channel length, thus increase transconductance, without lessening the on/off ratio. When non-percolating arrays of carbon nanotubes are linked via a semiconducting overlay, the majority of current paths between source and drain follow the highly conducting nanotubes with short, switchable semiconducting links completing the circuit. This field-induced percolating network allows for high transconductance with relatively large source—drain distance. Thus, transistors can be manufactured inexpensively by commercially available techniques using a variety of available semiconductors.

Large Area Flexible Electronics Fabricated Using Self-Aligned Imprint Lithography

This paper presents Self-Aligned Imprint Lithography (SAIL), a technology for producing submicron layer-to-layer alignments on large, dimensionally variable flexible plastic structures. The roll-to-roll compatible process is used to make 1 μm channel length transistors and active matrix arrays using a-Si and zinc-tin-oxide (ZTO) with electrical characteristics that nearly match those obtained using photolithography. The remaining issues for commercialization are discussed

Full-Swing Pentacene Organic Inverter with Long-Channel Driver and Short-Channel Load

As the channel length of pentacene organic thin-film transistors (OTFTs) is reduced, the transfer curve is consistently shifted to the positive direction and hence the drain current at the zero gate voltage increases, presumably due to the short-channel effect. By using this electrical characteristic, a full-swing organic inverter suitable for integrated organic circuits is demonstrated by combining the long-channel OTFT as an enhancement-mode driver and the short-channel OTFT as a depletion-mode load. Furthermore, the voltage transfer characteristics of the inverter can be optimized by the proper selection of the driver and load sizes.

Thin-film transistor realized with a combined active layer

A combined active layer thin-film transistor is reported. The effective channel length of this planar thin-film transistor is only 1.2μm, and no high resolution lithography technology is necessary for the fabrication processes. A discontinuous metal film is deposited on the semiconductor layer to form the combined active layer. The on-state current for a 3mm channel width is about 31mA, which is sufficient for most flat panel display devices.

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high- k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.

Pentacene-carbon nanotubes: Semiconducting assemblies for thin-film transistor applications

We demonstrate an alternative path for achieving high-transconductance organic transistors by assembling bilayers of pentacene onto random arrays of single-walled carbon nanotubes. We show here that, by varying the connectivity of the underlying nanotube network, the channel length of a thin-film transistor can be reduced by nearly two orders of magnitude—thus, enabling the increase of the device transconductance without reduction the on/off ratio. These field-induced percolating networks enable assembling high-transconductance transistors that, with relatively large source drain distances, can be manufactured with available commercial printing techniques.

A case study: power and performance improvement of a chip multiprocessor for transaction processing

Current high-end microprocessor designs focus on increasing instruction parallelism and clock frequency at the expense of power dissipation. This paper presents a case study of a different direction, a chip multiprocessor (CMP) with a smaller processor core than a baseline high-end 130-nm 64-bit SPARC server uniprocessor. We demonstrate that the size of the baseline processor core can be reduced by 2/3 using a combination of logical resource reduction and dense custom macros while still delivering about 70% of the TPC-C performance. Circuit speed is traded for power reduction by reducing the power supply from 1.0 to 0.8 V and increasing transistor channel lengths by 12.5% above the minimum. The resulting CMP with six reduced size cores and 4-MB L2 cache is estimated to run at 1.8 GHz while consuming less than 30% of the power compared to the scaled baseline dual-core processor running at 2.4 GHz. The proposed CMP is more than four times higher in TPC/W than the dual-core processor, facilitating the design of high-density servers.

The effects of device dimensions on the post-breakdown characteristics of ultrathin gate oxides

The effects of transistor channel length and width on post breakdown (BD) characteristics have been carefully investigated. As channel-length decreases, we have found that the probability of hard breakdown (HBD) increases and the soft breakdown (SBD) stability time decreases. However, these two quantities are found to be relatively insensitive to the channel width for long channel-length devices. Since SBD is unstable and finally causes the device failure, the so-called HBD prevalence ratio methodology has limitations which are particularly important in short-channel length devices. Our findings indicate that dimensional effects should be properly taken into account in the consideration of circuit reliability and for the application of any post-BD methodology.

Influence of source/drain contacts on sub‐micrometer organic field‐effect transistors

AbstractMeasured output characteristics of our prepared short‐channel organic transistor show the well known effect of a nonlinear increase of the drain current with positive curvature at low drain voltages. We investigated this peculiarity by means of 2D simulations considering the bilayer contact for source or drain, respectively. The simulations show that the low work function of the chromium adhesion layer causes the nonlinearity. Another important aspect demonstrated by the simulations is the estimation of the mobility applying the simple Shockley equation. The influence of the contact properties on the rise of the drain current results in erroneous values for the mobility as estimated directly from the current–voltage characteristics. Output characteristics of a 1 µm channel length transistor.magnified imageOutput characteristics of a 1 µm channel length transistor.(© 2005 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

High Mobility Pentacene Field Effect Transistors on Plastic

AbstractThis paper reports the electrical properties of thin-film transistors with pentacene active layers used in a bottom contact transistor geometry utilizing solution processed poly-4-vinylphenol (PVP) as the gate dielectric processed on a polyethylene napthalate (PEN) substrate. The transistors sometimes exhibit mobilities in excess of 1cm2/Vs. The effect of various surface treatments of the gate insulator, on the electrical properties of these transistors discussed. The development of photolithographically defined 2νm channel length bottom contact transistors is emphasized as the speed of circuit elements such as the rectifier scale inversely as the square of the channel length of the transistors. Surface cleaning and semiconductor deposition techniques that improve transistor characteristics and reduce hysteresis are evaluated and the variation of the ION/IOFF ratios with the different surface treatments is noted.

Source engineering in short channel double gate vertical SiGe-MOSFETs

Transistor channel lengths are being continually scaled to smaller dimensions to improve the high-frequency performance and package density, which will lead to the introduction of sub-50 nm gate lengths in production in the near future. In this paper, the performance of a double gate (DG) vertical metal oxide semiconductor field effect transistor (MOSFET) using strained-SiGe as the channel has been analyzed using simulation. The advantages of the band gap engineering and the vertical structure are shown in terms of (a) independence of channel length, (b) independence of source-drain bias, (c) improved device characteristics (lower off-current), (d) reduction of short channel effects, and (e) suitability for low-power operation.

An improved shift-and-ratio Leff extraction method for MOS transistors with halo/pocket implants

The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel length of the MOS transistors. The use of original shift-and-ratio method for L eff extraction of MOS transistors with halo/pocket implants results in systematic errors for L eff. In this paper a modification of the original method is proposed and its effectiveness is assessed through simulation. The values of L eff extracted by the proposed method are more reasonable than those obtained using the original shift-and-ratio method.

Fabrication and analysis of polymer field-effect transistors

Parameters of organic field-effect transistors (OFET) achieved in recent years are promising enough for R & D activities towards a commercial low-cost polymer electronics. In spite of the fast progress, preparations dominated by trial and error are concentrated essentially on higher mobility polymers and shorter channel patterning, and the analysis of measured data is based on oversimplified models. Here ways to professionalize the research on polymer field-effect transistors are discussed exploiting experience accumulated in microelectronics. First of all, designing the devices before fabricating and subsequently analyzing them requires appropriate modelling. Almost independently from the nature of the transport process, the device physics is basically described by the drift-diffusion model, combined with non-degenerate carrier statistics. Therefore, with a modified interpretation of the so-called effective density of states, existing simulation tools can be applied, except for special cases which are discussed. Analytical estimates are helpful already in designing devices, and applied to experimental data they yield input parameters for the numerical simulations. Preparations of OFET's and capacitors with poly(3-ocylthiophene) (P3OT), poly(3-dodecylthiophene) P3HT, Arylamino-poly-(phenylene-vinylene) (PPV), poly(2-methoxy, 5 ethyl (2′ hexyloxy) paraphenylenevinylene) MEH-PPV, and pentacene from a soluble precursor are described, with silicon dioxide (SiO2) or poly(4-vinylphenol) (P4VP) as gate insulator, and with rather different channel length. We demonstrate the advantage of combining all steps from design/fabrication to analysis of the experimental data with analytical estimates and numerical simulation. Of special importance is the connection between mobility, transistor channel length, cut-off frequency and operation voltage, which was the starting point for the development of a low-cost fabrication of high-performance submicrometer OFET's by an underetching technique. Finally results of simulation studies are presented concerning the formation of inversion layers, the influence of a trap distribution (as in the a-Si model) and of different types of source/drain contacts on top and bottom contact OFET's, and short-channel effects in submicrometer devices. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Effective Channel Length Shortening and Mobility Increase of p-Channel Metal Oxide Semiconductor Transistors Resulting in Higher Drive Current Using Short Source–Drain Diffusion Length

Local lattice strain around the channel in metal oxide semiconductor (MOS) transistors of 0.13 µm gate length using shallow trench isolation can be altered using different source–drain diffusion lengths (Lov). It is known that as Lov is reduced, the drive current of p-channel metal oxide semiconductor (PMOS) transistors can be increased due to stress-enhanced hole mobility. However, in this study, we found that as Lov is reduced below 0.62 µm, the effective channel length (Leff) of the PMOS transistors is also reduced. This unexpected Leff shortening effect for very small Lov has instead led to a reduction of µeff, as shown through our calculations. We thus propose that the drive current increase for Lov reduction is due to stress-enhanced hole mobility for larger Lov and that the Leff shortening due to stress-enhanced diffusion is the secondary and the more dominating mechanism for Lov values below 0.62 µm.