Transistor Channel Length Research Articles

Organic synaptic transistor showing ultralow energy consumption with a microscale channel by laser ablation

Low energy consumption per synaptic event is important for artificial synapses in applications of highly integrated and large-scale neuromorphic computing systems. Reducing the channel length of a synaptic transistor is an effective method to achieve this goal because such devices can work under low operating voltage and current. In this Letter, we use femtosecond laser ablation to fabricate a microscale slit in an Ag film as the channel of an organic synaptic transistor to obtain low energy consumption. The length of the shortest channel is only 1.6 μm. As a result, the device could be driven by a 50 μV drain bias voltage while output 855 pA excitatory postsynaptic current under a gate spike of 50 mV and 30 ms. The calculated energy consumption per synaptic event is 1.28 fJ, which is comparable to that of a biological synapse (1–10 fJ per synaptic event). Femtosecond laser ablation has been demonstrated a rapid and effective process for the fabrication of microscale channel with high resolution for synaptic transistor, showing large potential for the development of neuromorphic electronics.

Ultrashort vertical-channel MoS2 transistor using a self-aligned contact

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 105 and on-state current of 250 μA/μm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process.

Downsizing the Channel Length of Vertical Organic Electrochemical Transistors.

Organic electrochemical transistors (OECTs) are promising building blocks for bioelectronic devices such as sensors and neural interfaces. While the majority of OECTs use simple planar geometry, there is interest in exploring how these devices operate with much shorter channels on the submicron scale. Here, we show a practical route toward the minimization of the channel length of the transistor using traditional photolithography, enabling large-scale utilization. We describe the fabrication of such transistors using two types of conducting polymers. First, commercial solution-processed poly(dioxyethylenethiophene):poly(styrene sulfonate), PEDOT:PSS. Next, we also exploit the short channel length to support easy in situ electropolymerization of poly(dioxyethylenethiophene):tetrabutyl ammonium hexafluorophosphate, PEDOT:PF6. Both variants show different promising features, leading the way in terms of transconductance (gm), with the measured peak gm up to 68 mS for relatively thin (280 nm) channel layers on devices with the channel length of 350 nm and with widths of 50, 100, and 200 μm. This result suggests that the use of electropolymerized semiconductors, which can be easily customized, is viable with vertical geometry, as uniform and thin layers can be created. Spin-coated PEDOT:PSS lags behind with the lower values of gm; however, it excels in terms of the speed of the device and also has a comparably lower off current (300 nA), leading to unusually high on/off ratio, with values up to 8.6 × 104. Our approach to vertical gap devices is simple, scalable, and can be extended to other applications where small electrochemical channels are desired.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

Analysis on Contact Resistance and Effective Channel Length of Thin Film Transistors Using Composition-Modified In–Ga–Zn-O Active Channels Prepared with Atomic Layer Deposition and Various Electrode Materials

To verify the effects of process conditions for the TFTs employing In–Ga–Zn-O (IGZO) channels prepared by atomic layer deposition (ALD), such as cationic composition of channel and/or source/drain (S/D) electrodes, the device characteristics including the field-effect mobility (μFE), the contact resistance (RC), and the channel length deviation (ΔL) were systematically investigated for the ALD IGZO thin film transistors (TFTs) fabricated with controlling the ALD subcyclic ratios and with variations in S/D electrodes of indium–tin-oxide (ITO) and molybdenum (Mo). The ALD temperature was fixed at 200 °C. When the subcyclic ratios of precursors (triethyl indium: In–Ga bimetallic: diethyl zinc) were modulated to 0:2:2, 1:2:2, and 2:2:2, the cationic compositions (In:Ga:Zn) were determined to be 1.0:2.8:5.4, 1.0:1.1:2.3, and 1.0:0.7:1.5, respectively. As the the indium (In) contents within the IGZO channel increased from 5% to 14%, the μFE’s obtained from the TFTs using ITO and Mo S/D showed dramatic improvement from 16.1 to 36.9 cm2/(V s) and 2.8 to 20.1 cm2/(V s), respectively. For both sets of devices, the ΔL’s were estimated to be sensitively varied with channel compositions, and the RC markedly decreased owing to the reduction of barrier height formed at electrode/channel interfaces with increasing the In contents. The types of S/D electrodes also have a critical effect on the device performance. The devices using Mo S/D exhibited marked degradations in device characteristics rather than the devices using ITO S/D, which was suggested to originate from the additional formation of MoO3 layer at Mo/IGZO interfaces during the ALD process for the preparation of IGZO channel layers. Based on these findings, the intrinsic values of μFE for the ALD IGZO TFTs could be determined with considerations of RC and ΔL, especially for the devices with shorter channel lengths.

Tunneling leakage in ultrashort-channel MOSFETs—From atomistics to continuum modeling

The channel lengths of transistors are now nearing the nanometer, making these devices increasingly prone to direct source-to-drain tunneling (DSDT), a leakage mechanism commonly considered to set the end of Moore’s law. In MOSFETs, the probability for a charge carrier to undergo DSDT decays exponentially with channel length, source depletion length, and drain depletion length. Bound-charge engineering (BCE) is a recently introduced scheme where the depletion lengths of FETs can be controlled through effective doping by surface bound charges residing on the interface between a semiconductor and an adjacent oxide. In this letter, BCE is applied to reduce DSDT leakage current down to acceptable levels in MOSFETs with channels as short as 2.3nm; the higher the oxide permittivity, the lower the DSDT leakage. This idea is tested on ultrascaled Si nanowire MOSFETs via atomistic quantum transport simulations based on the nonequilibrium Green’s function (NEGF) formalism and the tight-binding model, as well as on physically larger Si nanosheet MOSFETs via continuum NEGF–k·p simulations based on the finite-element method.

P‐22: Effects of Self‐Assembled Monolayer on Contact Resistance Between IGZO and Electrode for High‐Resolution Display

We improved the contact properties by inserting a self‐assembled monolayer at the interface between a‐IGZO and metal electrode. For high‐resolution and high‐speed displays, the transistor channel length needs to be reduced without short channel effects. In case of Al electrode, it easily diffuses into a‐IGZO and forms AlOx at the interface, resulting in a considerable contact resistance increase. In our approach, we successfully suppressed Al diffusion by self‐assembled monolayer treatment on a‐IGZO thin film. The thickness of AlOx was significantly reduced, which was verified by transmission electron microscopy images. With a proper self‐assembled monolayer treatment, the contact resistance was decreased by 36%.

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

Ultralow‐Power and Multisensory Artificial Synapse Based on Electrolyte‐Gated Vertical Organic Transistors

AbstractBioinspired electronics have shown great potential in the field of artificial intelligence and brain‐like science. Low energy consumption and multifunction are key factors for its application. Here, multisensory artificial synapse and neural networks based on electrolyte‐gated vertical organic field‐effect transistors (VOFETs) are first developed. The channel length of the organic transistor is scaled down to 30 nm through cross‐linking strategy. Owing to the short channel length and extremely large capacitance of the electric double layer formed at the electrolyte–channel interface, the minimum power consumption of one synaptic event is 0.06 fJ, which is significantly lower than that required by biological synapses (1–10 fJ). Moreover, the artificial synapse can be trained to learn and memory images in a 5 × 5 synapse array and emulate the human brain's spatiotemporal information processing and sound azimuth detection. Finally, the artificial tongue is designed using the synaptic transistor that can discriminate acidity. Overall, this study provides new insights into realizing energy‐efficient artificial synapses and mimicking biological sensory systems.

Nanospike electrodes and charge nanoribbons: A new design for nanoscale thin-film transistors.

To scale down thin-film transistor (TFT) channel lengths for accessing higher levels of speed and performance, a redesign of the basic device structure is necessary. With nanospike-shaped electrodes, field-emission effects can be used to assist charge injection from the electrodes in sub–200-nm channel length amorphous oxide and organic TFTs. These designs result in the formation of charge nanoribbons at low gate biases that greatly improve subthreshold and turn-off characteristics. A design paradigm in which the gate electric field can be less than the source-drain field is proposed and demonstrated. By combining small channel lengths and thick gate dielectrics, this approach is also shown to be a promising solution for boosting TFT performance through charge focusing and charge nanoribbon formation in flexible/printed electronics applications.

Influence of Injection Barrier on Vertical Organic Field Effect Transistors

Organic field-effect transistors (OFETs) have shown great potential for applications that require low temperature deposition on large and flexible substrates. To increase their performance, in particular a high transconductance and transit frequency, the transistor channel length has to be scaled into the submicrometer regime, which can be easily achieved in vertical organic field effect transistors (VOFETs). However, despite high performance observed in VOFETs, these transistors usually suffer from short channel effects like weak saturation of the drain current and direct source-drain leakage resulting in large off currents. Here, we study the influence of the injection barrier at the source electrode on the OFF currents, on/off ratio, and transconductance of vertical OFETs. We use two semiconducting materials, 2,6-diphenyl anthracene (DPA), and C60 to vary the injection barrier at the source electrode and are able to show that increasing the Schottky barrier at the source electrode can decrease the direct source/drain leakage by 3 orders of magnitude. However, the increased injection barrier at the source electrode comes at the expense of an increased contact resistance, which in turn will decrease its transconductance and transit frequency. With the help of a 2D drift-diffusion simulation we show that the trade-off between low off currents and high transconductance is inherent to the current VOFET device setup and that new approaches have to be found to design VOFETs that combine good switching properties with high performance.

50.1: Invited Paper: Organic Thin‐Film Transistors with Mobility of 3cm2/Vs at L=5µm and a Process Temperature of 80 Degrees Celsius

Organic thin‐film transistor (OTFT) devices have been fabricated using a maximum processing temperature of 80°C making them suitable for a range of low‐cost transparent substrates. Charge mobility at transistor channel length (L) of 5 µm is up to 3cm2/Vs making OTFT suitable for a wide range of voltage or current driven display devices on plastic or glass. OTFT driven mini‐LED backlights are demonstrated showing 85,000 nits luminance making OTFT a viable technology for low‐cost HDR displays with high front of screen brightness.

A theoretical modeling analysis for triboelectrification controlled light emitting diodes

Abstract In this paper, we demonstrate the use of triboelectric nanogenerator (TENG) as a mean of mechanical light triggering to control InGaN-based light-emitting diodes (LEDs). Light extraction from the LED is two successive steps process. First, the voltage produced by the TENG is used to control the gate-to-source current of a MOSFET transistor through adjusting the transistor channel width and length. The second step is forwarding the drain-source current resulting from MOSFET transistor to the LED as its injection current to induce spontaneous emission from the LED surface to the air. Three LED colors are considered: red, green and blue. Significant emitted power from these InGaN-based LEDs in the RGB wavelength band is observed for both P-MOSFET and N-MOSFET transistor configurations. The emitted optical spectrum is controlled by optimizing the combined TENG-MOSFET-RGB LED geometry; dimensions and the bias voltage between the drain and source terminals of the MOSFET transistor. With recent advances in TENGs as an energy harvesting technology, it is expected that this study offers an approach to enhance the light extraction of various LED devices. With the enhancements in the performance of optoelectronic devices, the field of tribo-phototronics has attracted more attention, and in this work, we introduce the first theoretical framework, to the best of our knowledge, based on finite element modeling. This study provides significant insights into the working principles of tribo-Phototronic devices as well as guidelines for future device design.

Focused ion beam milling for the fabrication of 160 nm channel length IGZO TFTs on flexible polymer substrates

The quest for short channel length transistors is an important challenge in the semiconductor industry. A similar trend is observed in the field of flexible electronics where sensor conditioning circuits and transceivers have to be realized on plastic foils. Here the use of a focused Ga+ ion beam (FIB) to structure the channel of a flexible InGaZnO-based thin-film transistor (TFT) is presented. The resulting flexible TFT exhibits a channel length of and an effective field effect mobility of 4 cm2 V−1 s−1. Furthermore, the optimized Ga+ beam milling does not damage the Al2O3 gate insulator underneath, leading to a gate leakage current of <. The extreme channel length demonstrates that focused ion beams can complement conventional fabrication approaches, overcoming current limitations imposed by flexible substrates. While the dimensions result in short channel effects and a drain conductance of limiting the DC applicability of the FIB TFT, the device also exhibits a high internal gain of . Consequently, a transit frequency of ≈ and a maximum frequency of oscillation of ≈ is measured for supply voltages . This shows that highly scaled flexible TFTs for analog circuits can be fabricated by ion beam milling.

Taguchi DoE and ANOVA: A systematic perspective for performance optimization of cross-coupled channel length modulation OTA

This work is a demonstration of circuit optimization using Taguchi Design of Experiments. Cross coupled channel length modulation OTA has been considered for optimization. This optimization technique uses the concept of Signal to Noise Ratio (SNR) and Analysis of Variance (ANOVA) to predict which independent variable controls the performance of the circuit. Bias current, channel width and channel length of input transistors have been chosen to optimize the circuit performance. The obtained parameters for optimum performance from this method are verified by simulating the circuit using UMC 0.18 μm CMOS technology. The simulation results obtained are pretty close to the predicted solution from ANOVA. From simulation results, transconductance, power consumption, percentage total harmonic distortion, linearity range and DC gain of the proposed OTA are 24.63 nS, 1.026 μW, 0.347%, 1.09 V, and 54.88 dB respectively. The proposed optimized circuit, therefore, can be utilized in biomedical applications.

Schottky Barrier Variable Graphene/Multilayer-MoS2 Heterojunction Transistor Used to Overcome Short Channel Effects.

A single-layer MoS2 achieves excellent gate controllability within the nanoscale channel length of a field-effect transistor (FET) owing to an ultra-short screening length. However, multilayer MoS2 (ML-MoS2) is more vulnerable to short channel effects (SCEs) owing to its thickness and long screening length. We eliminated the SCEs in an ML-MoS2 FET (thickness of 4-13 nm) at a channel length of sub-30 nm using a Schottky barrier (SB) variable graphene/ML-MoS2 heterojunction. Although the band modulation in the ML-MoS2 channel worsens with a decrease in the channel length, which is similar to the SCEs occurring in conventional FETs, the variable Fermi level (EF) of a graphene electrode along the gate voltage allows control of the SB at the graphene/MoS2 junction and backs up the current modulation through a variable SB. Electrical measurements and a theoretical band simulation demonstrate the efficient SB modulation of our graphene nanogap (GrNG) ML-MoS2 FET with three distinct carrier transports along Vgs: a thermionic emission at a low SB, Fowler-Nordheim tunneling at a moderate SB, and direct tunneling at a high SB. Our GrNG FET shows an extremely high on-off current ratio of ∼108, which is approximately three-orders of magnitude better than a previously reported metal nanogap (MeNG) FET and a self-aligned metal/graphene nanogap FET with a similar MoS2 thickness. Our GrNG FET also exhibits a 100,000-times higher on-off ratio, 100-times lower subthreshold swing, and 10-times lower drain induced barrier.

Impact on Gain and Noise : ECG Amplifier &amp; Comb Filter Design using OTA

The research paper ventures a novel modelling strategy of finite gain and noise of an electrocardiogram (ECG) amplifier at 0.18, 0.5 and 0.9 micron standard CMOS technologies respectively. An active comb filter is used to design the amplifier for removing the selected frequencies of numerous signals. The presented filter is configured with only Operational Transconductance Amplifiers (OTAs) and capacitors that makes it apt for implementation of monolithic integrated circuits (ICs). The relevance of this analog circuit is verified for a suitable test signal of 60 Hz as in the ECG signal. Using Cadence Virtuoso analog design environment, the effect of transistor channel length and width is examined for analysis of noise and bandwidth. It is observed that the performance in terms of noise and gain considerably increases for advanced technology node. However, for a suitable supply of bias current, a portable ECG system can also provide an improved bandwidth performance of advanced CMOS technology.

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the Vdd and Vth values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore, process variation in sub-20 nm feature technologies introduces a substantial impact on speed and power. Thus, the impact of such variation on the scaled delay has to also be considered in the performance estimation. In this paper, we propose a system-level model to estimate this delay, taking into consideration voltage scaling under within-die process variation for both planar and FinFET CMOS transistors in the sub-20 nm regime. The model is simple, has acceptable accuracy and is particularly useful for architectural-level simulations for low-power design exploration at an early stage in the design space exploration. The proposed model estimates the delay in different supply voltage and threshold voltage ranges. The model uses a modified alpha-power equation to measure the delay of the critical path of a computational logic core. The targeted technology nodes are 14 nm, 10 nm, and 7 nm for FinFETs, and 22 nm, and 16 nm for planar CMOS. Within-die process variation is assumed to be lumped in with the threshold voltage and the transistor channel length and width to simplify its impact on delay. For the given technology nodes, the average percentage error numbers of theproposed delay equation compared to hSpice are between 0.5% to 14%.

Area-efficient all-digital pulse-shrinking smart temperature sensor with improved accuracy and resolution.

An all-digital CMOS (Complementary Metal-Oxide Semiconductor) pulse-shrinking smart temperature sensor (PSSTS) is proposed to deliver the merits of area efficiency, improved accuracy, and high resolution. First, an inverter-based temperature-sensing delay line generates a pulse with a width proportional to absolute temperature (PTAT). Then, a pulse-shrinking delay line (PSDL) with a pulse-mixing scheme (PMS) measures the PTAT pulse through pulse shrinking. The two delay lines become area efficient when the channel length of transistors is long. Conventionally, the area-efficient PSDL decreases the time resolution. Thus, the all-digital PMS considerably enhances the time resolution and achieves an excellent sensor resolution. Finally, a time subtractor improves sensor accuracy by effectively eliminating the offset error effects. The proposed sensor was implemented in a Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS process and occupied an area of 0.0247 mm2, which is the best area among related studies. The PSSTS exhibited an improved inaccuracy from a maximal inaccuracy of 1.95 °C to 1.5 °C and an excellent resolution of approximately 0.05 °C/LSB. Experimental results prove that this study is area-efficient and achieves improved accuracy and high resolution.

Recent Advances in Low‐Dimensional Heterojunction‐Based Tunnel Field Effect Transistors

AbstractSince the continuous scaling down of the transistor channel length, extraordinary improvement is achieved in the switching speed. However, the rising leakage current degrades the power consumption seriously. In this regard, reducing supply voltage might be the most effective method. This requirement can be fulfilled well by tunnel field‐effect transistors (TFETs), because carriers transport via a band‐to‐band tunneling manner in the TFETs. Relying on the special transport mechanism, the TFETs often require band structure modulations and steep interfaces without trap state, which are challenging for bulk materials. Therefore, these challenges have boosted TFET designs based on low‐dimensional materials ranging from Si/Ge nanowires to state‐of‐art van der Waals heterostructures. Here, the key concepts of the currently developed TFETs are studied from the aspects of structure, material, transportation characteristic, and mechanism. According to the heterojunction bonding types, they can be divided into lateral and vertical TFETs in general. Furthermore, other related transistors based on tunneling are also included. Emerging problems and promotion methods toward these TFETs are introduced with the assistance of simulations. The main goal is to introduce the frontiers of TFET explorations and provide readers with a perspective on how to realize TFET applications in the future.