Time-to-digital Converter Research Articles

Passive Electrical and Optical Methods of Ultra-Short Pulse Expansion for Event Timer-Based TDC in PPM Receiver

The energy efficiency of a communication system using pulse position modulation (PPM) can be increased by reducing the duration of the pulses transmitted over the communication channel to several tens of picoseconds. The employment of an event timer device as a time-to-digital converter (TDC) for demodulation allows the use of PPM with many pulse positions and achieves competitive data transfer speeds. However, along with several-picosecond accuracy of modern event timers, they require a pulse duration of several hundred picoseconds for precise detection. This research is devoted to developing passive techniques for precise pulse expansion from tens of picoseconds to hundreds of picoseconds. We propose two methods: the electrical method, which employs a microstrip low-pass filter (LPF), and the optical method, which uses fiber Bragg grating (FBG). This research offers a detailed analysis of distortion-free pulse expansion requirements, the design of prototypes meeting these requirements, and experimental design verification. Theoretical background, mathematical models, and results of experimental validation of the proposed pulse expansion methods within the laboratory transmitted reference pulse-position modulation (TR-PPM) communication system are provided.

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal’s jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.

A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz.

A 2.5 pJ/bit PVT-Tolerant True Random Number Generator Based on Native-NMOS-Regulated Ring Oscillator

In this brief, an energy-efficient true random number generator (TRNG) is presented based on the jitter noise of a single ring oscillator (RO). By XORing two different oscillation stages of the RO, consecutive pulses can be generated due to the fixed intrinsic propagation delay and more importantly, the time-varying jitter-noise-caused variation to the above delay. By continuously quantizing the above pulses’ width using another high-frequency RO-based time-to-digital converter (TDC), the TDC’s least significant bits (LSBs) are dominated by the jitter noise, of which the magnitude can be largely increased through reducing the RO’s supply voltage with a native NMOS transistor. Based on a 40-nm standard CMOS process, the proposed TRNG design is fabricated and extensively characterized. By passing the widely-exploited test tools of National Institute of Standards and Technology (NIST) and autocorrelation function, the proposed TRNG’s randomness has been well validated. Moreover, the randomness evaluation is further extended to various process-voltage-temperature (PVT) conditions, and the measured Shannon entropy is always larger than 0.999995, showing excellent PVT tolerance. Finally, the proposed TRNG features a high energy efficiency of 2.5 pJ/bit at a throughput of 53 Mbps.

A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters.

We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from -75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs' performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications.

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

This paper presents a high-density,129-channel, dual-‘hit’ FPGA-based time-to-digital converter (TDC) developed to implement the trigger-less data acquisition (DAQ) system for the Iron Calorimeter (ICAL) detector of the India-based Neutrino Observatory (INO) experiment. In this trigger-less DAQ scheme, the arrival time of signals from all the detector channels, about 3.6 million channels in the case of the INO-ICAL experiment, is required to be measured. This work, therefore, aimed at the development of a low-power, high-density TDC with uniform performance across the channels in the low-cost Spartan-6 FPGA. This TDC is based on tapped delay line (TDL) interpolation technique built using CARRY4 elements of the FPGA in the Spartan-6 FPGA-based DAQ system. In this TDC, a method for measuring the time-of-arrival of both the rising edge and subsequent falling edge (dual-hit) using a single channel is developed, thus allowing pulse width measurements. Here, a resource and power-aware design methodology is developed to arrive at the optimum values of the total number of delay elements in the TDL and clock frequency, facilitating the implementation of a large number of identical TDC channels. Further, in order to meet the area and timing constraints of the high-density TDC, semi-automatic placement scripts are developed with careful partitioning of the TDC channels. These aspects resulted in an implementation of the TDC with a least significant bit (LSB) resolution of 84.4 ps ± 2.5 ps, a dynamic range of 40 μs, time precisions (σ) across the channels in the range of 42 ps (0.49 LSB) to 58 ps (0.68 LSB), differential nonlinearity (DNL) of ±0.5 LSB and integral nonlinearity (INL) of [-0.49,0.84] LSB with a low power consumption of 7 mW per channel.

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm ^2$</tex-math> </inline-formula> . With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm _w$</tex-math> </inline-formula> ) is 24.4 fJ/conversion-step.

Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method

The time-to-digital converter (TDC) is the primary instrument for measuring time intervals. A common solution for FPGA-based TDCs is to construct a tapped delay line (TDL) for time interpolation to produce a sub-clock time resolution. The jitter and quantization, granularity and uniformity of the delay cells, and so on in TDL, determine the achievable TDC time resolution and linearity. To achieve higher linearity, a TDL and its encoding method for compact TDC on the UltraScale FPGA is proposed in this paper. A dual-sampling method with TDL is adopted, which improves precision and efficiency by directly encoding the state of the delay line, allowing further subdivision of the delay unit in combination with wave union. The bin width of the TDL obtained based on our method is measured here using the code density calibration method and draw the integral nonlinearity and differential nonlinearity. Based on the chain structure and encoding method proposed in this article, the TDL and encoding layout have been optimized to achieve a more compatible UltraScale FPGA and can also be further applied to multi-channel TDC.

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exploits the internal routing resources available in the FPGA as delay elements. A manual placement and routing technique that results in greater resolution and linearity is proposed. The time-interleaving concept is used to improve the resolution of the TDC. A measurement matrix with 512 and 1024 parallel counters is implemented on a Zynq Evaluation and Development (ZED) board. The result of the 1024-unit TDC showed that a dynamic range of 93.6 ns can be measured using a 4-bit coarse gray code counter running at a reference frequency of 171 MHz, and a resolution of 5.7 ps is achieved. The implemented TDC is low-cost, has a fast time to market, and it benefits from the abundant routing resources in the FPGA.

Temperature Sensor with Buffer-Chain based Time-to-Digital Converter for Ultra-Low Voltage Operation

This paper proposes a Time-to-Digital Converter (TDC) based temperature sensor that aims to operate with an ultra-low voltage electromotive force for IoT applications with energy harvesting. Sub-threshold circuit design was exploited for the operation at ultra-low supply voltage. The proposed circuit uses the characteristics of leakage current for temperature measurement. The virtual ground node in the proposed sensor is charged up by leakage current and the charging time changes with the temperature. To measure the temperature-dependent charging time, we used a buffer-chain based TDC to achieve ultra-low voltage operation. Simulation results demonstrated that the minimum supply voltage for the proposed circuit is 0.15V. The power consumption is 407nW and sensing time is 180ns at 25℃. The measurable temperature range is from -40℃ to 85℃. The proposed circuit was designed with Renesas SOTB 65nm process. Simulation evaluation was conducted using HSPICE.

A 256 × 256 LiDAR Imaging System Based on a 200 mW SPAD-Based SoC with Microlens Array and Lightweight RGB-Guided Depth Completion Neural Network.

Light detection and ranging (LiDAR) technology, a cutting-edge advancement in mobile applications, presents a myriad of compelling use cases, including enhancing low-light photography, capturing and sharing 3D images of fascinating objects, and elevating the overall augmented reality (AR) experience. However, its widespread adoption has been hindered by the prohibitive costs and substantial power consumption associated with its implementation in mobile devices. To surmount these obstacles, this paper proposes a low-power, low-cost, single-photon avalanche detector (SPAD)-based system-on-chip (SoC) which packages the microlens arrays (MLAs) and a lightweight RGB-guided sparse depth imaging completion neural network for 3D LiDAR imaging. The proposed SoC integrates an 8 × 8 SPAD macropixel array with time-to-digital converters (TDCs) and a charge pump, fabricated using a 180 nm bipolar-CMOS-DMOS (BCD) process. Initially, the primary function of this SoC was limited to serving as a ranging sensor. A random MLA-based homogenizing diffuser efficiently transforms Gaussian beams into flat-topped beams with a 45° field of view (FOV), enabling flash projection at the transmitter. To further enhance resolution and broaden application possibilities, a lightweight neural network employing RGB-guided sparse depth complementation is proposed, enabling a substantial expansion of image resolution from 8 × 8 to quarter video graphics array level (QVGA; 256 × 256). Experimental results demonstrate the effectiveness and stability of the hardware encompassing the SoC and optical system, as well as the lightweight features and accuracy of the algorithmic neural network. The state-of-the-art SoC-neural network solution offers a promising and inspiring foundation for developing consumer-level 3D imaging applications on mobile devices.

Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power Quantum Entanglement Detection

Quantum microscopy requires efficient detectors able to identify temporal correlations among photons. Photon coincidences are usually detected by postprocessing their timestamps measured by means of time-to-digital converters (TDCs), through a time and power-consuming procedure, which impairs the overall system performance. In this article, we propose an innovative single-photon sensitive imager based on single-photon avalanche diodes (SPADs), able to signal coincident photon pairs along with their position through a TDC-free, event-driven architecture. The result is a highly efficient detector (25.8%) with a 100% duty cycle and minimized data throughput. The modular architecture and the 330 ns readout time, independent of pixel number, pave the way to large format imagers based on the same paradigm. The detector enabled quantum imaging at extremely low, microwatt-level optical pump powers, four orders of magnitude lower than previous experiments with similar optical setups.

Reconfigurable coaxial single-photon LIDAR based on the SPAD array.

The single-photon avalanche diode (SPAD) array with time-to-digital converter (TDC) circuits on each pixel is an excellent candidate detector for imaging LIDAR systems. However, the low fill-factor of the SPAD array does not allow for efficient use of laser energy when directly adopted in a LIDAR system. Here, we design a reconfigurable coaxial single-photon LIDAR based on the SPAD array and diffractive optical elements (DOEs). We use the DOE and beam expander to shape the laser beam into a laser dot matrix. The total divergence angle of the DOE spot beam is strictly matched to the total field of view (FOV) angle of the SPAD array. Meanwhile, each focused beamlet is individually matched to every active area of the SPAD array detector, which increases the use of output energy about 100 times compared to the diffusion illumination system. Besides, the system uses the active area as the minimum pixel and can support sub-pixel scanning, resulting in higher resolution images. Through this coaxial structure, two different telescope systems after transceiver switching can be reconfigured for imaging targets at different distances. Based on our single-photon LIDAR system, we achieved 3D imaging of targets at 100m and 180m using two different telescope configurations.

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method.

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.

PicoTDC: a flexible 64 channel TDC with picosecond resolution

The PicoTDC is a 64 channel TDC (Time to Digital Converter) ASIC, with 3ps or 12ps time binning, developed at CERN for use in a large variety of high channel count scientific instrumentation. Acquired time measurements are processed on-chip with a programmable buffering and triggered data flow architecture before being read out on 1 to 4 byte-wise readout ports with a total readout bandwidth of up to 10 Gbps. Leading edge, falling edge or leading edge together with pulse width can be captured at burst rates as high as 1.2 GHz and sustained rate of 320 MHz per channel. Effective single-shot time resolution has been measured to be 3.7 ps RMS across all 64 channels over its full dynamic range and as good as 1.35 ps RMS when using an on-chip adjustment feature optimized for a specific channel (0.43 ps if averaged over multiple measurements). The PicoTDC is implemented in a 65 nm CMOS process and 20 k chips have been produced and packaged in a 400 pin plastic BGA package.

Design of a high-accuracy time-to-digital converter based on dual-edge signals

Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge “1” count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81,0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33,2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73,0.98] LSB0 and [-2.46,1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

A Low-Cost Measurement Methodology for LiDAR Receiver Integrated Circuits

This paper presents a test methodology to facilitate the measuring processes of LiDAR receiver ICs by avoiding the inherent walk error issue. In a typical LiDAR system, a costly laser diode driver emits narrow light pulses with fast rising edges, and the reflected pulses from targets enter an optical detector followed by an analog front-end (AFE) circuit. Then, the received signals pass through the cascaded amplifiers down to the time-to-digital converter (TDC) that can estimate the detection range. However, this relatively long signal journey leads to the significant decline of rising-edge slopes and the output pulse spreading, thus producing inherent walk errors in LiDAR receiver ICs. Compensation methods requiring complex algorithms and extra chip area have frequently been exploited to lessen the walk errors. In this paper, however, a simpler and lower-cost methodology is proposed to test LiDAR receiver ICs by employing a high-speed buffer and variable delay cells right before the TDC. With these circuits, both START and STOP pulses show very similar pulse shapes, thus effectively avoiding the walk error issue. Additionally, the time interval between two pulses is easily determined by varying the number of the delay cells. Test chips of the proposed receiver IC implemented in a 180-nm CMOS process successfully demonstrate easier and more accurate measurement results.

Optimizing Time Resolution Electronics for DMAPs

Depleted Monolithic Active Pixel Sensors (DMAPSs) are foreseen as an interesting choice for future high-energy physics experiments, mainly because of the reduced fabrication costs. However, they generally offer limited time resolution due to the stringent requirements of area and power consumption imposed by the targeted spatial resolution. This work describes a methodology to optimize the design of time-to-digital converter (TDC)-based timing electronics that takes advantage of the asymmetrical shape of the pulse at the output of the analog front-end (AFE). Following that methodology, a power and area efficient implementation fully compatible with the RD50-MPW3 solution is proposed. Simulation results show that the proposed solution offers a time resolution of 2.08 ns for a range of energies from 1000 e− to 20,000 e−, with minimum area and zero quiescent in-pixel power consumption.

JitSCA: Jitter-based Side-Channel Analysis in Picoscale Resolution

In safety and security conscious environments, isolated communication channels are often deemed necessary. Galvanically isolated communication channels are typically expected not to allow physical side-channel attacks through that channel. However, in this paper, we show that they can inadvertently leak side channel information in the form of minuscule jitter on the communication signal. We observe worst-case signal jitter within 54 ± 45 ps using an FPGA-based receiver employing a time-to-digital converter (TDC), which is a higher time resolution than a typical oscilloscope can measure, while in many other systems such measurements are also possible. A transmitter device runs a cryptographic accelerator, while we connect an FPGA on the receiver side and measure the signal jitter using a TDC. We can indeed show sufficient side-channel leakage in the jitter of the signal by performing a key recovery of an AES accelerator running on the transmitter. Furthermore, we compare this leakage to a power side channel also measured with a TDC and prove that the timing jitter alone contains sufficient side-channel information. While for an on-chip power analysis attack about 27k traces are needed for key recovery, our cross-device jitter-based attack only needs as few as 47k traces, depending on the setup. Galvanic isolation does not change that significantly. That is an increase by only 1.7x, showing that fine-grained jitter timing information can be a very potent attack vector even under galvanic isolation. In summary, we introduce a new side-channel attack vector that can leak information in many presumably secure systems. Communication channels can inadvertently leak information through tiny timing variations, known as signal jitter. This could affect millions of devices and needs to be considered.