A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

Abstract

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.