Time-to-digital Converter Research Articles

Design and Implementation of Low Power Time-To-Digital Converter using MGDI Technique

This paper introduces a novel Time to Digital Converter (TDC) architecture based on the Modified Gate Diffusion Input (MGDI) technique, which is derived from the well-established GDI method. Through the utilization of MGDI-based logic gates and digital circuitry, this innovative approach leads to a substantial reduction in the number of transistors required for implementation. As a result, it offers significant advantages in terms of circuit area, power consumption, and propagation delay, while simultaneously simplifying the complexity of the overall logic design. The functional blocks within the TDC have been optimized to efficiently process an internal clock frequency of 5MHz. This achievement is realized using cutting-edge 90nm MGDI technology, operating at a supply voltage of 1V. Practical implementation of this design can be carried out seamlessly with Cadence Virtuoso tools in the 90nm technology node. In essence, this research effort represents a promising advancement in the realm of time-to-digital conversion. By harnessing the capabilities of MGDI and its transistor-saving attributes, the proposed TDC not only enhances performance but also addresses critical concerns such as power efficiency and chip area utilization. These advancements make it a compelling choice for applications requiring precise time measurements, while the compatibility with contemporary technology nodes ensures its relevance and applicability in modern integrated circuit design.

A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC

This paper presents a 16-way time-interleaved (TI) time-domain (TD) analog-to-digital converter (ADC) with full multiplexing of hardware resources and highly synchronous reconfigurable from 8-to-10-bit 20-to-5-GS/s accuracy and speed for multi-standard communication systems. A gain reconfigurable voltage-to-time converter (VTC) with high-precision RF sampling circuitry is proposed to achieve an input bandwidth greater than 18 GHz and an SFDR of 49.93 dB in 20-GS/s mode. The high-resolution, low-jitter time-to-digital converter (TDC) exploits ring-oscillation (RO) dual-channel multiplexing to mitigate inter-channel mismatch and introduces a time-amplifier (TA) based on the discharge time difference to determine the order of the rising edge corresponding to the differential signal. Fabricated in a 40-nm CMOS process, the ADC can be configured as a 5-GS/s 10-b, 10-GS/s 9-b, or 20-GS/s 8-b converter. It demonstrates the 50.81-/46.67-/36.79-dB SNDR and 56.42-/54.59-/45.77-dB SFDR at the Nyquist input frequencies corresponding to the three modes mentioned above, with the power consumption of 83.6-/103.7-/139.3-mW contributing to Walden figure-of-merit (FoMW) value of 59.0-/58.9-/123.4- fJ/conversion-step.

An FPGA-based 500 M samples per second throughput time-to-digital converter without ineffective bin

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) are widely studied because of their attractive performance. However, tapped-delay-line (TDL) length variation and TDL over-length caused by ineffective bins will degrade performance of multi-channel TDCs. This article proposes an FPGA-based multi-channel dual-mode TDC, which is not suffered from TDL length variation and TDL over-length. The proposed TDC uses a dual-mode toggling input stage and inner FIFOs to realize 500 M samples per second throughput in 2μs. A dual-mode encoder and a valid-sampling controller are particularly designed for dual-mode implementation to resolve TDL length variation and TDL over-length. The presented TDC is implemented in an FPGA device of 28 nm technology, and integrated in a time measurement system. Experimental results show that there is no ineffective bin in the proposed TDC’s TDLs. The average root-mean-square (RMS) resolutions of the “0” mode and the “1” mode are 15.7 ps and 15.4 ps respectively.

A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process

ABSTRACT The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC’s post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs.

A Low-Cost Test Method for Accurate Detection of Different Excited-State Species with a Lifetime Span over 5 Orders of Magnitude in One Time Window

Accurate quantification on the quantum yields (φ) of both the prompt fluorescence (PF) and the delayed fluorescence (DF) species is quite essential for the clarification of molecular design rationales for thermally activated delayed fluorescence (TADF) luminogens. Currently, most φPF and φDF data of TADF fluorophores were acquired through time-correlated single-photon counting (TCSPC) lifetime measurement systems. However, because of their equal-time-channel working manner, so far all the commercially available TCSPC systems cannot render accurate measurement on φPF of TADF materials due to the lack of enough valid data points in the faster decay region of the corresponding photoluminescence (PL) decay curves. Although an intensified charge coupled device (ICCD) system equipped with a streak camera or an optical parametric oscillation laser has been proven to be a powerful tool for accurate determination of φPF and φDF of TADF fluorophores, the ultrahigh cost of these ICCD systems makes them inaccessible to most users. Herein, by replacing the timing module of a commercial TCSPC system with a low-cost and versatile time-to-digital converter (TDC) module, we developed a modified TCSPC system that can work in an unequal-time-channel manner. The resultant TDC-TCSPC system can not only concurrently determine the accurate lifetime of PF and DF species whose lifetime span even exceeds 5 orders of magnitude in just one time window but also render accurate measurements on φPF and φDF of TADF fluorophores. The reliability of the TDC-TCSPC method was verified through TCSPC- and ICCD-based comparative experiments on ACMPS, a known TADF fluorophore. Our results not only can provide a low-cost and convenient test method for accurate determination of key experimental data of TADF materials but also will facilitate deeper understanding of the molecular design principles for high-performance TADF materials.

CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy

A 256-channel single-photon avalanche diode (SPAD) line sensor was designed for time-resolved Raman spectroscopy in 110-nm CMOS technology. The line sensor consists of an 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 256 SPAD array and 256 parallel connected time-to-digital converters (TDCs). The adjustable temporal resolution and dynamic range of TDCs are 25.6–65 ps and 3.2–8.2 ns, respectively. The median timing skew along 256 channels is 43.7 ps, and TDC bin boundaries can be fine-tuned at the ps-level to enable precise timing skew compensation. The sensor is capable of real-time dark count measurement (two dark measurements for each excitation pulse) that gives accurate data for dark count compensation without any increment in measurement time. The maximum excitation pulse rate with real-time dark count measurement is 680 kHz. Raman spectra of six different samples were measured to prove the performance of the sensor in time-resolved Raman spectroscopy.

An Integrated-Circuit Node for High-Spatiotemporal Resolution Time-Domain Near-Infrared Diffuse Optical Tomography Imaging Arrays

Next-generation brain–computer interfaces (BCIs) for healthy individuals are expected to largely rely on noninvasive functional imaging methods to record cortex-wide neural activity because of the risk associated with surgically implanted devices. In this work, we present a fully integrated 1.8 × 1.8 mm single chip that can be arrayed on a wearable patch to perform noninvasive, functional brain imaging over large cortical areas. This chip node contains two bonded vertical-cavity surface-emitting lasers (VCSELs), an 8 × 8 single-photon avalanche diode (SPAD) array with event-driven time-to-digital converters (TDCs) per row, and a digital back-end for on-chip histogramming and time-gating. We achieved 70-ps resolution for time-of-flight (ToF) imaging at the record-high 100-MHz laser repetition rate with 80-mW total power. We showed that time-gating improves the imaging contrast by as much as 36% using a brain-skull phantom. The fully integrated and compact node presented here is the key enabler for future high-spatiotemporal-resolution time-domain diffuse optical tomography (TD-DOT) imaging arrays.

A dual Mössbauer spectrometer for material research, coincidence experiments and nuclear quantum optics

A newly developed dual Mössbauer spectrometer with an integrated time-to-digital converter (TDC) is described in detail. This spectrometer enables variety of Mössbauer experiments in the transmission, emission and resonant configuration as well as coincidence experiments and time differential Mössbauer spectroscopy (TDMS). The device allows investigation of gamma pulses, gamma echos or quantum beats. Thus, it is suitable not only for material research but also for nuclear quantum optics. The dual spectrometer also brings new possibilities to Mössbauer spectroscopy such as an easy determination of a Lamb–Mössbauer factor. The wide functionality of the device comes from an employment of a microcontroller together with FPGA, which is utilized for TDC implementation and a fast signal processing. The performance of the developed spectrometer is demonstrated on several experiments.

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW

Compact, high-bandwidth analog-to-digital converters (ADCs) with moderate resolution are a critical building block in high-speed communication links. In this work, a hybrid time and voltage domain ADC is presented that uses a single high-speed voltage-to-time converter (VTC) as a high-bandwidth sampling buffer for a four-way time-interleaved successive approximation (SAR) ADC. Time-domain encoding also enables a low-power 3b SAR assist time-to-digital converter (TDC) to enhance SAR speed with minimal calibration. A 0.0045 mm2 prototype fabricated in 22 nm fin field-effect transistor (FinFET) CMOS provides 13 GHz effective resolution bandwidth (ERBW) and consumes 6.0 mW with a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 38 dB at 3.8 GS/s, for 24.4 fJ/step Walden FoM.

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.

Time-to-digital conversion techniques: a survey of recent developments

Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for digital processing of analog signals encoded in time. Since design of time-mode circuits facilitates replacing analog blocks with digital circuitry, TDCs pave the way to hardware-efficient and purely digital architectures in deep-submicron semiconductor technology. The design and implementation of modern TDCs is heterogeneous, shaped in multiple directions, and driven by CMOS process downscaling along with application demands. The substantial research effort is made in more intensive digital implementations, optimization of techniques for high resolution, increasing input range and linearity, reduced conversion time, power consumption and silicon area. The calibration and mismatch-tolerant, as well as anti-PVT-variation and anti-metastability design techniques are of growing importance in order to alleviate imperfections of nanoscale CMOS technologies. The paper surveys recent developments of time-to-digital conversion techniques to give a possibly comprehensive picture of major trends and design advancements. Finally, we highlight TDC design challenges for cutting-edge applications such as All-Digital Phase Locked Loops for high data rate wirelesss communication systems operating in the millimeter-wave band.

A low-power DTOF image sensor with double-frame-multiplexing mode for long-range detection

A novel time-to-digital converter (TDC) operation mode, called double-frame-multiplexing (DFM), is proposed for time-of-flight (TOF) measurements. It is based on the separate detection of the minimum distance and depth of the measured targets, which reduces the power consumption of in-pixel TDCs and expands the maximum detection distance under high resolution. A 64 × 64 direct TOF image sensor chip is fabricated in a 0.18 μm CMOS process. Driven by a 125 MHz multi-phase clock and a 50 MHz data readout clock, the chip achieves a maximum frame rate of 20 kframe/s, a maximum detection distance of 750 m (5 μs), and a maximum depth of field of 3 m (20 ns) with a temporal resolution of 1 ns. The DFM mode reduces the average power consumption to 60 mW without consideration of SPADs. The worst-case measured differential nonlinearity is −0.61/+0.69 least significant bit (LSB) and the maximum integral nonlinearity is −1.06/+0.66 LSB.

Towards a Multi-Pixel Photon-to-Digital Converter for Time-Bin Quantum Key Distribution.

We present an integrated single-photon detection device custom designed for quantum key distribution (QKD) with time-bin encoded single photons. We implemented and demonstrated a prototype photon-to-digital converter (PDC) that integrates an 8 × 8 single-photon avalanche diode (SPAD) array with on-chip digital signal processing built in TSMC 65 nm CMOS. The prototype SPADs are used to validate the QKD functionalities with an array of time-to-digital converters (TDCs) to timestamp and process the photon detection events. The PDC uses window gating to reject noise counts and on-chip processing to sort the photon detections into respective time-bins. The PDC prototype achieved a 22.7 ps RMS timing resolution and demonstrated operation in a time-bin setup with 158 ps time-bins at an optical wavelength of 410 nm. This PDC can therefore be an important building block for a QKD receiver and enables compact and robust time-bin QKD systems with imaging detectors.

A dToF Ranging Sensor with Accurate Photon Detector Measurements for LiDAR Applications.

Direct time-of-flight (dToF) ranging sensors based on single-photon avalanche diodes (SPADs) have been used as a prominent depth-sensing devices. Time-to-digital converters (TDCs) and histogram builders have become the standard for dToF sensors. However, one of the main current issues is the bin width of the histogram, which limits the accuracy of depth without TDC architecture modifications. SPAD-based light detection and ranging (LiDAR) systems require new methods to overcome their inherent drawbacks for accurate 3D ranging. In this work, we report an optimal matched filter to process the raw data of the histogram to obtain high-accuracy depth. This method is performed by feeding the raw data of the histogram into the different matched filters and using the Center-of-Mass (CoM) algorithm for depth extraction. Comparing the measurement results of different matched filters, the filter with the highest depth accuracy can be obtained. Finally, we implemented a dToF system-on-chip (SoC) ranging sensor. The sensor is made of a configurable array of 16 × 16 SPADs, a 940 nm vertical-cavity surface-emitting laser (VCSEL), an integrated VCSEL driver, and an embedded microcontroller unit (MCU) core to implement the best matched filter. To achieve suitably high reliability and low cost, the above-mentioned features are all packaged into one module for ranging. The system resulted in a precision of better than 5 mm within 6 m with 80% reflectance of the target, and had a precision better than 8 mm at a distance within 4 m with 18% reflectance of the target.

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented as a chain of fast carry propagation multiplexers. In FPGAs, the fast carry chains are constrained to dedicated logic and routing, and need to be routed strictly vertically. In this work, we present an alternative approach to designing on-chip voltage sensors, in which the FPGA routing resources replace the carry logic. We present three variants of what we name a routing delay sensor (RDS): one vertically constrained, one horizontally constrained, and one free of any constraints. We perform a thorough experimental evaluation on both the Sakura-X side-channel evaluation board and the Alveo U200 datacenter card, to evaluate the performance of RDS sensors in the context of a remote power side-channel analysis attack. The results show that our best RDS implementation in most cases outperforms the TDC. On average, for breaking the full 128-bit key of an AES-128 cryptographic core, an adversary requires 35% fewer side-channel traces when using the RDS than when using the TDC. Besides making the attack more effective, given the absence of the placement and routing constraint, the RDS sensor is also easier to deploy.

Design and Implementation of Two-Stage Time-to-Digital Converter Based on Rapid Single-Flux-Quantum Circuits

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

FPGA-Based Time-to-Digital Converter for Pulsed Laser Ranging

This paper implements a Time-to-digital Converter (TDC) in a field-programmable gate array (FPGA), which is made for a single-photon-counting-based pulsed laser ranging system. The fine time is measured by the Tapped Delay Line (TDL) constructed in an internal dedicated carry chain of the FPGA. The length of the TDC is longer than one clock period, and the whole CARRY4 is utilized as a delay unit. The proposed TDC is made up of the fine time measurement module, encoder, coarse time counter, and data transport module, which are achieved in a resource-tensed FPGA Xilinx-ZYNQ. As this paper is done in a shared FPGA, the presented TDC can replace the ASIC-TDC GP22 as the TOF measurement module. By measuring the same time interval and modifying the fixed error in TDC, the results show that the time resolution can reach 53 ps. Compared with the ASIC-TDC GP22, both linearity and measurement range are improved in the proposed TDC, which makes the pulsed laser ranging system more flexible and integrated.

Development and test of a next-generation positron detector

This report is focused on the development and test of a TDC (time to digital converter) and amplifier circuit for a state-of-the-art positron detector with position sensitivity. A newly developed one chip amplifier-shaper-discriminator (ASD) circuit with 16 channels input and a high-resolution TDC with a timing resolution on the order of picoseconds were tested. Silicon photomultipliers (SiPMs) were employed to give electric pulses for the optical input coming from a pulsed laser. We have successfully controlled the threshold level of the ASD circuit and measured the time structure of the SiPMs, as well as their multiple photon response from the pulse height histogram and the time over the threshold (TOT) histogram measured by the sub-nano second TDC. This is a technical basis for the next generation detector system with the positron tracking capability.

A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells

Time-to-digital converters (TDCs) are commonly used for on-chip instrumentation. This article proposes a low-cost Cyclic-TDC with several distinct features. It can adapt to the process variation to maintain a fine resolution across all process corners. This is made possible by a so-called one-way varactor cell (OWVC) and an autonomous calibration process. In addition, it supports easy process migration. Last but not least, we show how it can be used for clock jitter measurement with reduced output uncertainty. Simulation results using a 90-nm CMOS process and a 40-nm CMOS process are used to demonstrate their advantages.

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

A digital phase-locked loop (DPLL) using the feedforward phase-error cancellation (FPC) is presented. The phase error of this DPLL using a digitally controlled ring oscillator is quickly canceled by a digitally controlled delay line (DCDL), which improves the phase noise performance. The loop gain of this FPC DPLL is also calibrated. In addition, a dead-zone-free (DZF) bang-bang phase-frequency detector (BBPFD) is presented to enhance the resolution of the time-to-digital converter (TDC). This proposed DPLL is fabricated in a 40-nm CMOS process which occupies 0.05 mm2. The measured rms jitter integrated from 1 kHz to 100 MHz is 788 fs at 1.6 GHz. The measured reference spur is −57.84 dBc for a 50 MHz reference frequency. Its power consumption is 5 mW for a 1.1-V supply voltage.