Abstract
This paper presents a 16-way time-interleaved (TI) time-domain (TD) analog-to-digital converter (ADC) with full multiplexing of hardware resources and highly synchronous reconfigurable from 8-to-10-bit 20-to-5-GS/s accuracy and speed for multi-standard communication systems. A gain reconfigurable voltage-to-time converter (VTC) with high-precision RF sampling circuitry is proposed to achieve an input bandwidth greater than 18 GHz and an SFDR of 49.93 dB in 20-GS/s mode. The high-resolution, low-jitter time-to-digital converter (TDC) exploits ring-oscillation (RO) dual-channel multiplexing to mitigate inter-channel mismatch and introduces a time-amplifier (TA) based on the discharge time difference to determine the order of the rising edge corresponding to the differential signal. Fabricated in a 40-nm CMOS process, the ADC can be configured as a 5-GS/s 10-b, 10-GS/s 9-b, or 20-GS/s 8-b converter. It demonstrates the 50.81-/46.67-/36.79-dB SNDR and 56.42-/54.59-/45.77-dB SFDR at the Nyquist input frequencies corresponding to the three modes mentioned above, with the power consumption of 83.6-/103.7-/139.3-mW contributing to Walden figure-of-merit (FoMW) value of 59.0-/58.9-/123.4- fJ/conversion-step.
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