A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process

Abstract

ABSTRACT The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC’s post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs.