An FPGA-based 500 M samples per second throughput time-to-digital converter without ineffective bin

Abstract

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) are widely studied because of their attractive performance. However, tapped-delay-line (TDL) length variation and TDL over-length caused by ineffective bins will degrade performance of multi-channel TDCs. This article proposes an FPGA-based multi-channel dual-mode TDC, which is not suffered from TDL length variation and TDL over-length. The proposed TDC uses a dual-mode toggling input stage and inner FIFOs to realize 500 M samples per second throughput in 2μs. A dual-mode encoder and a valid-sampling controller are particularly designed for dual-mode implementation to resolve TDL length variation and TDL over-length. The presented TDC is implemented in an FPGA device of 28 nm technology, and integrated in a time measurement system. Experimental results show that there is no ineffective bin in the proposed TDC’s TDLs. The average root-mean-square (RMS) resolutions of the “0” mode and the “1” mode are 15.7 ps and 15.4 ps respectively.