A Resource-saving Method for Implementation of High-Performance Time-to-Digital Converters in FPGA

Abstract

In field programmable gate array (FPGA) based time-to-digital converters (TDC), the prevailing time interpolation is propagating the hit signal along the tapped delay line (TDL), which status is sampled to be encoded as the sub-clock timestamp. The TDLs in all current TDC designs have lengths that guarantee the total propagating time on TDLs larger than one system clock period, which results in a more complicated encoder and unnecessary logic resource consumption. In this paper, we propose to shorten the TDL length by half and combine it to a novel bubble-proof encoding scheme with an aim to make the TDC resource-saving without losing any performance. Such two identical TDC channels have been implemented in a Xilinx Kintex-7 FPGA. Their performances are evaluated with an average RMS precision of 9.7 ps for measuring time-intervals from 0 to 20 ns and the measurement throughput of 277 M events per second, which are equivalent to the TDCs implemented in our previous work using the long TDLs. The consumption of logic resources is demonstrated to be 80% of the original. This resource-saving advantage of the proposed TDC is important to applications that require highly integrated multi-channel TDC systems.