Through Silicon Via Structure Research Articles

Employing Thermal Oxidation and Through-Silicon Via Technologies in CuO-Based Sensors for Room-Temperature NO2 Detection

We present the development and characterization of room-temperature CuO gas sensor fabricated through a thermal oxidation process complemented by a through-silicon via (TSV) structure. The TSV structure is a tapered hole with the top width measuring approximately 190 um and narrowing to 103 um at the bottom. The CuO film serves as the sensing material, with its predominant (111) orientation confirmed through X-ray diffraction analysis. Transmission electron microscopy analysis indicated lattice spacing of 0.23 nm within the CuO samples, corresponding to the (111) plane. Sensor performance was evaluated at a room temperature of 25 °C, showing response rates of 19.3%, 34.6%, 39.3%, and 46.3% to NO2 concentrations of 0.5, 1, 2, and 5 ppm, respectively. Stability testing of the sensor at 1 ppm NO2 concentration across five cycles demonstrated a consistent response around 34.6% with a deviation of less than 2%. The CuO material exhibited enhanced selectivity for NO2 over other gases such as NH3, CO2, CO, H2, H2S, and SO2.

Fatigue behaviour analysis of thermal cyclic loading for through-silicon via structures based on backstress stored energy density

Through-silicon via (TSV) structures are widely used in microelectronic due to the ease of chip interconnection. Few research has focused on investigating the fatigue properties of TSV structures using crystal plasticity finite element (CPFE) simulations. As the process of TSV structures approaches the micron scale, the effects of anisotropic microstructure and grain size on their fatigue behaviours will become necessary. The present work aims to use CPFE simulations to investigate the fatigue properties of TSVs at the microscale. Finite element models with realistic EBSD morphology and orientation are established for four TSV structures with different grain sizes, and CPFE simulations with thermal cyclic loading from −55℃ to 125℃ are performed. From the energy point of view, the stored energy density based on backstress and strain gradient is proposed as a fatigue indicator parameter (FIP). CPFE simulation results show that low-angle grain boundaries (LAGBs) and high-angle grain boundaries (HAGBs) dominate crack initiation at the top, bottom or edges of the TSV structure, which is still mainly due to the thermal mismatch effect caused by the difference in the coefficients of thermal expansion of the materials. The crack initiation in the internal structure is mainly caused by symmetric grains containing twin boundaries (TBs), or trigrain boundaries, and this is different from the macroscopic simulations. Combined with the local FIPs concentration distribution, the backstress stored energy density is able to capture more details than the cumulative plastic strain because of its direct correlation with the strain gradient, and validates its effectiveness as a FIP.

Design of a Novel Compact Bandpass Filter Based on Low-Cost Through-Silicon-Via Technology.

Three-dimensional (3D) integration based on through-silicon-via (TSV) technology provides a solution to the miniaturization of electronic systems. In this paper, novel integrated passive devices (IPDs) including capacitor, inductor, and bandpass filter are designed by employing TSV structures. For lower manufacturing costs, polyimide (PI) liners are used in the TSVs. The influences of structural parameters of TSVs on the electrical performance of the TSV-based capacitor and inductor are individually evaluated. Moreover, with the topologies of capacitor and inductor elements, a compact third-order Butterworth bandpass filter with a central frequency of 2.4 GHz is developed, and the footprint is only 0.814 mm × 0.444 mm. The simulated 3-dB bandwidth of the filter is 410 MHz, and the fraction bandwidth (FBW) is 17%. Besides, the in-band insertion loss is less than 2.63 dB, and the return loss in the passband is better than 11.4 dB, showing good RF performance. Furthermore, as the filter is fully formed by identical TSVs, it not only features a simple architecture and low cost, but also provides a promising idea for facilitating the system integration and layout camouflaging of radio frequency (RF) devices.

Modeling and Validation of Total Ionizing Dose Effect on the TSVs in RF Microsystem.

Radio frequency (RF) systems utilizing through-silicon vias (TSVs) have been widely used in the aerospace and nuclear industry, which means that studying the total ionizing dose (TID) effect on TSV structures has become necessary. To investigate the TID effect on TSV structures, a 1D TSV capacitance model was established in COMSOL Multiphysics (COMSOL), and the impact of irradiation was simulated. Then, three types of TSV components were designed, and an irradiation experiment based on them was conducted, to validate the simulation results. After irradiation, the S21 degraded for 0.2 dB, 0.6 dB, and 0.8 dB, at the irradiation dose of 30 krad (Si), 90 krad (Si), 150 krad (Si), respectively. The variation trend was consistent with the simulation in the high-frequency structure simulator (HFSS), and the effect of irradiation on the TSV component was nonlinear. With the increase in the irradiation dose, the S21 of TSV components deteriorated, while the variation of S21 decreased. The simulation and irradiation experiment validated a relatively accurate method for assessing the RF systems' performance under an irradiation environment, and the TID effect on structures similar to TSVs in RF systems, such as through-silicon capacitors.

Wearable Multi-Channel Pulse Signal Acquisition System Based on Flexible MEMS Sensor Arrays with TSV Structure.

Micro-electro-mechanical system (MEMS) pressure sensors play a significant role in pulse wave acquisition. However, existing MEMS pulse pressure sensors bound with a flexible substrate by gold wire are vulnerable to crush fractures, leading to sensor failure. Additionally, establishing an effective mapping between the array sensor signal and pulse width remains a challenge. To solve the above problems, we propose a 24-channel pulse signal acquisition system based on a novel MEMS pressure sensor with a through-silicon-via (TSV) structure, which connects directly to a flexible substrate without gold wire bonding. Firstly, based on the MEMS sensor, we designed a 24-channel pressure sensor flexible array to collect the pulse waves and static pressure. Secondly, we developed a customized pulse preprocessing chip to process the signals. Finally, we built an algorithm to reconstruct the three-dimensional pulse wave from the array signal and calculate the pulse width. The experiments verify the high sensitivity and effectiveness of the sensor array. In particular, the measurement results of pulse width are highly positively correlated with those obtained via infrared images. The small-size sensor and custom-designed acquisition chip meet the needs of wearability and portability, meaning that it has significant research value and commercial prospects.

Thermodynamic Multi-Field Coupling Optimization of Microsystem Based on Artificial Intelligence

An efficient multi-objective optimization method of temperature and stress for a microsystem based on particle swarm optimization (PSO) was established, which is used to map the relationship between through-silicon via (TSV) structural design parameters and performance objectives in the microsystem, and complete optimization temperature, stress and thermal expansion deformation efficiently. The relationship between the design and performance parameters is obtained by a finite element method (FEM) simulation model. The neural network is built and trained in order to understand the mapping relationship. Then, the design parameters are iteratively optimized using the PSO algorithm, and the FEM results are used to verify the efficiency and reliability of the optimization methods. When the optimization target of peak temperature, bump temperature, TSV temperature, maximum stress and maximum thermal deformation are set as 100 °C, 55 °C, 35 °C, 180 Mpa and 12 μm, the optimization results are as follows: the peak temperature is 97.90 °C, the bump temperature is 56.01 °C, the TSV temperature is 31.52 °C, the maximum stress is 247.4 Mpa and the maximum expansion deformation is 11.14 μm. The corresponding TSV structure design parameters are as follows: the radius of TSV is 10.28 μm, the pitch is 65 μm and the thickness of SiO2 is 0.83 μm. The error between the optimization result and the target temperature is 2.1%, 1.8%, 9.9%, 37.4% and 7.2% respectively. The PSO method has been verified by regression analysis, and the difference between the temperature and deformation optimization results of the FEM method is not more than 3%. The stress error has been analyzed, and the reliability of the developed method has been verified. While ensuring the accuracy of the results, the proposed optimization method reduces the time consumption of a single simulation from 2 h to 70 s, saves a lot of time and human resources, greatly improves the efficiency of the optimization design of microsystems, and has great significance for the development of microsystems.

An analytical thermal model for the 3-D integrated circuit with new-type through silicon via

Through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit (3-D IC), which can transfer heat from multiple dies to the heat sink in vertical direction. In this paper, a new gen?eral model of the through-silicon via (TSV) is proposed to investigate the thermal performance of the 3-D IC. The heat transfer characteristics of conical-annular TSV are studied for the first time. The impacts of different sidewall inclination angles and insulating layer thicknesses of TSV on the heat dissipation of 3-D IC were compared and analyzed in detail. As expected, our proposed model is in good agreement with the results of the existing models, which shows that the proposed model considering the lateral heat transfer and TSV structures can predict the distribution of temperature more efficiently and accurately. Furthermore, it is found that conical-annular TSV has more excellent heat dissipation performance.

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

Through-silicon-via (TSV)-based coaxial line techniques can reduce the high-frequency loss due to the low resistivity in the silicon substrate and thus can improve the efficiency of vertical signal transmission. Moreover, a TSV-based coaxial structure allows easily realizing the impedance matching in RF/microwave systems for excellent electrical performance. However, due to the limitations of existing available dielectric materials and the difficulties and challenges in the manufacturing process, ideal coaxial TSVs are not easy to obtain, and thus, the achieved electrical performance might be unexpected. In order to increase the flexibility of designing and manufacturing TSV-based coaxial structures and to better evaluate the fabricated devices, modeling and analysis theories of the corresponding high-frequency electrical performance are proposed in the paper. The theories are finally well validated using the finite-element simulation results, hereby providing guiding rules for selecting materials and improving manufacturing techniques in the practical process, so as to optimize the high-frequency performance of the TSV structures.

A TSV-Structured Room Temperature p-Type TiO2 Nitric Oxide Gas Sensor

Planar MOS/MEMS gas sensors have been widely studied and applied, but the detection of exhaled gas has been little developed. The flow rate of exhaled gas affects the suspension structure of the MEMS gas sensor and the operating temperature of the gas sensor. Therefore, this study uses the Bosch process and the atomic layer deposition (ALD) process to prepare a room-temperature (RT) TSV-structured TiO2 gas sensor. The results indicated that the TiO2 sensing film is uniformed and covers the through-silicon via (TSV) structure and the TiO2 sensing film is confirmed to be a p-type MOS. In terms of gas sensing at room temperature, the response of the sensor increases with the increasing NO concentration. The sensor response is 16.5% on average, with an inaccuracy of <± 0.5% for five cycles at 4 ppm NO concentration. For gas at 10 ppm, the response of the sensor to NO is 24.4%, but the sensor produces almost no response to other gases (CO, CO2, SO2, and H2S). The RT TiO2 gas sensor with a TSV structure exhibits good stability, reversibility, and selectivity to NO gas.

Experimental research on performance degradation of TSV microstructure under thermal cycling, vibration and electrical stress

Through‑silicon-via (TSV) microstructure is the key structure of 3D integrated packaging, and its reliability during service plays a very important role in the long-term reliable operation of the chip. However, the failure mechanism and reliability evaluation of the TSV structure in the service process of the chip have not been fully elucidated. Chips inevitably bear various stresses during the service process, such as thermal stress, vibration stress, electrical stress, etc. In this paper, a TSV reliability test chip that can be easily loaded with various stresses was designed first, and the resistivity of the TSV microstructure was tested. It is found that the resistivity of TSV has a significant scale effect. Then, thermal cycling, vibration and electromigration tests were carried out, and the failure mode, performance degradation trend and failure distribution of TSV microstructure under thermal cycling, vibration and electrical stress were analyzed. Finally, the failure analysis of the tested chip was carried out by scanning electron microscope (SEM) and high-resolution industrial micro-CT, and the potential failure mechanism were analyzed and discussed.

Microstructure evolution and mechanical behavior of copper through‑silicon via structure under thermal cyclic loading

The through‑silicon via (TSV) technique is widely applied in the latest highly integrated circuits packaging. However, one of the prevalent failure modes is caused by thermal cyclic loading from power fluctuations of the chip. Different thermal expansion coefficients of Cu and Si could cause a mismatch of thermal stresses under temperature cycling, which will lead to thermal fatigue failure of structure. In the current study, thermal cycling experiments are performed on Cu-TSV samples to investigate the effect of temperature cycling on microstructure evolution and mechanical behavior. The electron backscatter diffraction analysis is conducted to investigate the grain size, local texture and microstructure evolution of Cu. Based on the crystal plasticity theory, a constitutive model considering temperature and grain size effect is developed, and the parameters are calibrated. Combining crystal plasticity theory and finite element analysis, the effects of grain orientation and different grain sizes on the stress distribution and plastic work evolution of TSV structure under thermal cyclic loading are investigated.

Effects of multi-cracks and thermal-mechanical coupled load on the TSV reliability

Three-dimensional (3D) integrated packaging technology is gradually moving from the laboratory to the market. Through silicon via (TSV) is the most critical structural unit in 3D integrated packaging. However, during the TSV manufacturing process flow and its service process, many micro cracks will be generated in the TSV microstructure. The multi-cracks seriously threaten the reliability of the TSV and affect the device performance and service life. The existing literature often focus on a single crack under thermal load alone, which obviously does not match the actual situation and leads to larger analysis errors. Based on the theory of elastoplastic fracture mechanics and multi-physics coupling analysis, this paper explored the effects of multi-cracks and thermal-mechanical coupled load on the reliability of TSVs using numerical analysis. Using the J integral value as the indicator, the effects of crack numbers, crack locations, crack lengths, crack propagation directions and thermal-mechanical coupled load on the crack propagation of TSV structures were studied. Based on the research results, suggestions were made for TSV structure design and manufacturing process optimization. The main goal of this paper is to explore the influence of cracks and thermal-mechanical coupled loads on TSV microstructure through numerical analysis. Due to the micro-scale of the TSV structure, the above targets are difficult to obtain through experimental tests. The research methods and results of this paper can provide important references for the reliability evaluation and optimization design of TSV microstructures.

Crosstalk Noise of Octagonal TSV Array Arrangement Based on Different Input Signal

This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end and differential signal) by using a coplanar wave guide (CPW) testing structure. These results, based on traditional TSV arrays, show that a staggered TSV layout with differential signals had lower crosstalk noise. On this basis, the octagonal layout of TSV array is proposed and we show that it has obvious superiority in reducing occupied silicon area and crosstalk noise. Compared with traditional TSV arrays, the crosstalk noise is almost reduced by 44%. In order to further reduce the silicon area occupied by TSV without worsening crosstalk noise, the new division TSV structure is proposed in which a large TSV was substituted by four smaller TSVs. The area occupied by a single TSV and TSV array are both reduced by 60% without decreasing signal integrity when the regular TSV in the octagonal layout are replaced by a new TSV structure.

Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

Study on atomic migration of copper through-silicon-vias with Bosch scallops

In three-dimensional integration, atomic migration is a critical challenge for through‑silicon-via (TSV) reliability, especially under high electric current and thermal stress. Meanwhile, Bosch scallops, as the byproduct of Bosch process, can cause stress concentration around them, which further undermines TSV reliability. In this paper, the migration behavior of copper TSVs with Bosch scallops is assessed in an operational scenario using a migration model, while residual stress is taken into account. The possible failure location is studied first, followed by the mechanism of different migration modes. It is shown that the effect of stress on atomic migration manifests itself earlier than that of electric current. Besides, the periodic concentration fluctuation arises along the interface with Bosch scallops, and the amplitude of fluctuation increases as the width of Bosch scallops increases. Furthermore, the impacts of operation temperature and process temperature are investigated to guide the optimization design for the robust TSV structure.

Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe.

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs

Through Silicon Vias (TSVs) are crucial elements for the reliable operation and yield of three dimensional integrated circuits (3D ICs). Defects are a serious concern in TSV structures. A post-bond, parallel testing and diagnosis scheme is proposed in this work, for the detection and location of resistive open or short to substrate defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing method provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical model simulations and Monte-Carlo analysis results, using the 65 nm technology of TSMC, prove the effectiveness of the new method. Additionally, two representative methods from the literature are simulated and compared to the proposed one, in terms of effectiveness, robustness, tolerance, cost and design for testability effort. The proposed scheme is proven to perform better based on all presented criteria.

Thermal–Mechanical Performance Analysis and Structure Optimization of the TSV in 3-D IC

The through-silicon via (TSV) technology is widely used in 3-D integrated circuit (3-D IC) devices. However, the TSV could cause great thermal stress due to the mismatch of the thermal expansion between different materials, which affects the performance of the 3-D IC. In this work, a finite element model of the 3-D IC device with both internal pin-fin microchannels and all-copper interconnection is established. A substructure model is further developed and validated against the results obtained from the full model. Then, the thermal-mechanical performances of the TSV structure under thermal cycling loads are investigated based on the substructure model. The results show that the maximum stress locates at the edge of the interface between TSV_copper and memory, and the deformation on the TSV_copper-memory interface is dominated by shearing, which may cause the debonding of the interface. Moreover, the influences of the TSV structure parameters on the maximum thermal stress and TSV_copper's electrical resistance are analyzed. Then, the TSV structure is further optimized to reduce the stress and improve the electrical conductivity. Compared with the original design, the maximum von Mises stress and TSV_copper resistance of the optimized structure can be reduced by 18.4% and 40.6%, respectively.

Inhibiting the detrimental Cu protrusion in Cu through-silicon-via by highly (111)-oriented nanotwinned Cu

Cu protrusion phenomenon, one of the biggest challenges of the Cu through-silicon-via (TSV) technology, results from the thermal stress accumulation and the following plastic deformation during thermal annealing. Herein, we proposed an effective approach to inhibiting the detrimental Cu protrusion by introducing a highly (111)-oriented nanotwinned Cu to the TSV structure. The Cu nanotwin structure, in comparison with the normal Cu structure, gave rise to a 70.3% decrement of the protrusion height during thermal annealing at 250°C. The protrusion inhibition was attributed to the effective interaction of high-fraction coherent nanotwin boundaries with dislocations. The presence of low-energy coherent twin boundaries impeded dislocation glide, giving rise to the TSV strengthening and the significant protrusion inhibition. The electrodeposited nanotwinned Cu TSV exhibited great thermal stability under thermal annealing at 250°C for 2 h, as evidenced by the slight micro-hardness loss, 6.7%, based on the nanoindentation analysis.

Low-loss through silicon Vias (TSVs) and transmission lines for 3D optoelectronic integration

The optoelectronic hybrid integration based on co-package has attracted much attention to meet the requirements of high-performance chip development and functional integration. TSVs and redistribution layers (RDLs) are of great importance for both the packaging process and the system design of 3D integration. This paper presents the measurements and analysis of TSV and RDL test structures, from DC to high frequency up to 67 GHz. TSVs and RDLs with low insertion loss up to 67 GHz are demonstrated and the impact of TSV arrangements on the transmission performance are analysed. The insertion loss of a 500 μm long coplanar waveguide (CPW) transmission line of frontside RDL (FSRDL) is 0.75 dB at 67 GHz. The insertion loss is less than 1 dB at 67 GHz for a TSV-RDL signal path with the length of 500 μm.