Experimental research on performance degradation of TSV microstructure under thermal cycling, vibration and electrical stress

Abstract

Through‑silicon-via (TSV) microstructure is the key structure of 3D integrated packaging, and its reliability during service plays a very important role in the long-term reliable operation of the chip. However, the failure mechanism and reliability evaluation of the TSV structure in the service process of the chip have not been fully elucidated. Chips inevitably bear various stresses during the service process, such as thermal stress, vibration stress, electrical stress, etc. In this paper, a TSV reliability test chip that can be easily loaded with various stresses was designed first, and the resistivity of the TSV microstructure was tested. It is found that the resistivity of TSV has a significant scale effect. Then, thermal cycling, vibration and electromigration tests were carried out, and the failure mode, performance degradation trend and failure distribution of TSV microstructure under thermal cycling, vibration and electrical stress were analyzed. Finally, the failure analysis of the tested chip was carried out by scanning electron microscope (SEM) and high-resolution industrial micro-CT, and the potential failure mechanism were analyzed and discussed.