Through Silicon Via Structure Research Articles

Inhibiting the detrimental Cu protrusion in Cu through-silicon-via by highly (111)-oriented nanotwinned Cu

Cu protrusion phenomenon, one of the biggest challenges of the Cu through-silicon-via (TSV) technology, results from the thermal stress accumulation and the following plastic deformation during thermal annealing. Herein, we proposed an effective approach to inhibiting the detrimental Cu protrusion by introducing a highly (111)-oriented nanotwinned Cu to the TSV structure. The Cu nanotwin structure, in comparison with the normal Cu structure, gave rise to a 70.3% decrement of the protrusion height during thermal annealing at 250°C. The protrusion inhibition was attributed to the effective interaction of high-fraction coherent nanotwin boundaries with dislocations. The presence of low-energy coherent twin boundaries impeded dislocation glide, giving rise to the TSV strengthening and the significant protrusion inhibition. The electrodeposited nanotwinned Cu TSV exhibited great thermal stability under thermal annealing at 250°C for 2 h, as evidenced by the slight micro-hardness loss, 6.7%, based on the nanoindentation analysis.

Low-loss through silicon Vias (TSVs) and transmission lines for 3D optoelectronic integration

The optoelectronic hybrid integration based on co-package has attracted much attention to meet the requirements of high-performance chip development and functional integration. TSVs and redistribution layers (RDLs) are of great importance for both the packaging process and the system design of 3D integration. This paper presents the measurements and analysis of TSV and RDL test structures, from DC to high frequency up to 67 GHz. TSVs and RDLs with low insertion loss up to 67 GHz are demonstrated and the impact of TSV arrangements on the transmission performance are analysed. The insertion loss of a 500 μm long coplanar waveguide (CPW) transmission line of frontside RDL (FSRDL) is 0.75 dB at 67 GHz. The insertion loss is less than 1 dB at 67 GHz for a TSV-RDL signal path with the length of 500 μm.

Microfluidic Device for In Situ Observation of Bottom-Up Copper Electrodeposition in a TSV-Like Structure

Using a microfluidic device with a replica TSV (Through Silicon Via) structure, in situ observation of the copper via filling was made. Although the bottom-up TSV filling is possible by electroplating with a combination of several additives, the mechanism of bottom-up filling is not yet clear. Observation of the filling behavior is important, and cross sectioning of the TSVs is widely used. But the sectioning process takes some time, and continuous observation of the progress of deposition is difficult. In this study, a replica TSV structure was constructed in a microchannel, and real-time observation using the microfluidic device took place. As an example, extreme bottom-up filling obtained with addition of the leveler was monitored, and the effect of the immersion time before the plating, and progress of electrodeposition toward the via opening, were demonstrated. The observed deposition behavior was discussed in terms of the diffusion-adsorption model, and moderate agreement of the initial locations of deposition between the experiments and a simple 1-d numerical model estimate was obtained.

Effects of anisotropy on the reliability of TSV microstructure

Through silicon via (TSV) is a very important interconnect structure in 3D integrated packaging, and its reliability directly affects the reliable service life of 3D integrated packaging devices. TSVs contain multiple material interfaces, and there is a large thermal mismatch between the materials, which poses a serious challenge to its reliability under thermal cycling loads. In the available literatures, silicon (substrate) and copper (filler) materials have often been considered as isotropic materials for research and analysis. However, for micron-scale TSV structures, the orientation of silicon crystals and the orientation of copper grains can have a non-negligible effect on the stress and strain distribution and interface crack propagation of the structure, which in turn significantly affects the overall reliability of the TSV structure. This article explored in detail the influence of the anisotropy of silicon and copper on the reliability of TSVs, and particularly focused on the coupled effect of anisotropic of silicon and copper. In addition, the influence of copper plasticity was also analyzed.

Stress evolution mechanism and thermo-mechanical reliability analysis of copper-filled TSV interposer

Through silicon via (TSV) has become one of the key emerging trends of three-dimensional (3D) packages, as it can realize vertically interconnect between stacked-dies. Due to large mismatch in thermal expansion coefficients (CTE) between the copper via and the silicon, significant mechanical stresses are induced at the interfaces when TSV structure is subjected to thermal stresses, which would greatly affect the reliability and electrical performance of TSV 3D device. In this paper, the relationship between the state of stresses and failure of TSV had been explored by combining finite element model simulation (FEM) and failure physical analysis. The position of the maximum stress of the TSV structure was obtained by FEM analysis. The relationship of stress and displacement change with temperature was also studied. And a thermal cycling experiment was conducted to validate the simulation results. Physical failure analysis after thermal cycling experiment was used to verify the degradation mechanism predicted by thermo-mechanical simulation.

Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC

The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on-chip interconnects has been demonstrated. Subsequently, a novel time-efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through-silicon-via (TSV), which is used to connect different dies vertically in a 3D IC. Under high-frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

Research on fatigue of TSV-Cu under thermal and vibration coupled load based on numerical analysis

The three-dimensional (3D) integrated packaging technology based on through-silicon-via (TSV) is recognized as a new packaging technology which is most likely to exceed Moore's Law and complies with the requirements of smaller size, higher performance, lighter weight and lower power consumption. However, its failure mechanism and reliability problems during the long-term service process have not been fully elucidated, which hinders its widespread application. There is plenty of literature about the reliability of the TSV structure under thermal load, but the literature considering vibration loads is extremely rare. On the other hand, most of the previous literature focuses on the reliability of the TSV structure in manufacturing processes (such as annealing), but little attention was paid to their reliability assessment during service life. As the fundamental structure of 3D integrated packaging, TSV reliability will undoubtedly play a pivotal role in the long-term service reliability of the chip. The TSV structure needs to withstand various complex loads during service, such as thermal load, vibration load, electric load, etc., so it is necessary to consider the coupling of various loads to scientifically and effectively evaluate its reliability life. In this paper, the fatigue theory and multi-field coupled numerical analysis theory were summarized in detail. On this basis, a numerical analysis method for thermal-vibration coupling of TSV copper (TSV-Cu) was proposed. The typical TSV microstructure model was established and the fatigue life of electroplated copper under thermal and vibration coupled loads was calculated based on E-N curve. The influence of loading parameters on fatigue life was explored and compared. The results show that the effects of different load forms and parameter conditions on the fatigue life of TSV-Cu are significantly different.

Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions.

The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.

Electromagnetic analysis for optical coherence tomography based through silicon vias metrology.

This paper reports on progress in the analysis of time-domain optical coherence tomography (OCT) applied to the dimensional metrology of through-silicon vias (TSVs), which are vertical interconnect accesses in silicon, enabling three-dimensional (3D) integration in microelectronics, and estimates the deviations from earlier, simpler models. The considered TSV structures are 1D trenches and circular holes etched into silicon with a large aspect ratio. As a prerequisite for a realistic modeling, we work with spectra obtained from reference interferograms measured at a planar substrate, which fully includes the dispersion of the OCT apparatus. Applying a rigorous modal approach, we estimate the differences to a pure ray tracing technique. Accelerating our computations, we focus on the relevant fundamental modes and apply a Fabry-Perot model as an efficient approximation. Exploiting our results, we construct and present an iterative procedure based on the minimization of a merit function, which concludes TSV heights reliably, accurately, and rapidly from measured interferograms.

Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation

As a 3D integration technology, the through silicon via (TSV) has attracted increasing interest owing to the need for reducing energy consumption in devices. However, high thermal stress is induced owing to large mismatches in the coefficients of thermal expansion (CTE) between the copper via and the silicon (Si) substrate in TSVs, causing critical reliability issues such as the performance degradation of stress-sensitive devices. We proposed a novel structure, the annular-trench-isolated (ATI) TSV, as a possible solution for the reliability issues caused by thermal stress in 3D packaging technology with TSVs. The ATI TSV structure has an extra Si ring outside of the metal core. We successfully fabricated an ATI TSV with a 10-μm diameter using separate etching processes for the insulator trench and the metal core. A narrow insulator trench with a thickness of 2 μm was formed, and its aspect ratio (AR) was as high as 10. A Si ring with a thickness of 1 μm remained between the insulator layer and the metal core. In order to study the stress level of the ATI TSV, we investigated the radial and axial thermal stresses using polarized Raman spectroscopy and a simulation by the Finite Element Method. Agreement between the simulation results and the measured stress data was observed and validated the simulation model. Furthermore, we revealed that the Si substrate of the ATI TSV had a lower thermal stress level than the regular TSV. This was accomplished using the validated simulation model owing to the redistribution of stress by the Si ring in the ATI TSV.

Study of the Influence of Elastic Anisotropy of Cu on Thermo-Mechanical Behavior and Cu Protrusion of Through Silicon Vias Using Combined Phase Field and Finite Element Methods

Drastic reduction in the diameter of the Cu-filled through silicon via (TSV) leads to the TSV feature size becoming comparable with the grain size in the Cu filler, and accordingly Cu grain characteristics strongly influence thermo-mechanical behavior and Cu protrusion of the TSV due to the elastic anisotropy of Cu, which poses new emerging issues and challenges for reliability analysis of the TSV. In this paper, a 2-D phase field model is combined with a finite element model to study comprehensively and quantitatively the grain morphology characteristics, thermo-mechanical behavior and Cu protrusion in a typical Cu-filled TSV structure, while considering the mechanical property anisotropy of Cu. Results show that Cu grains with different orientations make distinct contributions to the deformation behavior of the Cu filler which undergoes three stages of deformation, that is, elastic, elasto-plastic, and plastic as temperature increases, consequently resulting in the anisotropic thermo-mechanical behavior of the Cu-filled TSV and the dependence of Cu protrusion on the average grain size of the Cu filler. Moreover, both the average von Mises stress and equivalent plastic strain of the Cu filler decrease with the increase in Cu grain size, and the average von Mises stress in fine grains is higher than that in coarse grains. Furthermore, Cu protrusion decreases with the increase of the average size of Cu grains. However, for limited grains in the Cu-filled TSV, the average von Mises stress, equivalent plastic strain, and Cu protrusion increase with an increase in the average size of Cu grains.

Extracting Radio Frequency Properties of a Typical Through-Silicon Via Structure With a Self-Developed Deembedding Technique

The parasitic effect inside through-silicon via (TSV) packaging under radio frequency (RF) operation may cause abnormal signals in circuit performance. On the bases of a self-developed deembedding technique, we investigated the high-frequency characteristics of a typical TSV structure through direct measurements. To this end, a silicon substrate layout was first designed and constructed, followed by packaging mounting to build a suitable setting for RF measurements. Behaviors up to 3 GHz on different circuit segments in an actual TSV packaging were then measured directly by using an RF-inductance, capacitance, and resistance (LCR) meter, and R, L, and impedance (Z) data for test structures were then extracted and compared with those reported in the literature. To study the environmental effect on the RF properties of the TSV test samples, we monitored behaviors during a temperature-humidity reliability test.

Study on copper protrusion of through-silicon via in a 3-D integrated circuit

The through-silicon via (TSV) approach is crucial for three-dimensional integrated circuit (3-D IC) packaging technology. However, there are still several challenges in the TSV fabrication process. One of the widely known challenges is via protrusion phenomenon. Annealing a TSV wafer makes the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is extruded out of the TSV structure. The phenomenon occurs because of the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) layer. Cu protrusion is able to cause crack, delamination of the back-end-of-line and short circuit of the chip, thus, it is a dangerous threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscope is used to observe the protrusion topography and measure the height. Electron backscatter diffraction (EBSD) technique is implemented to study the grain size distribution, local texture and microstructure evolution inside Cu vias. For the experiment, arrays of 10 μm diameter TSVs are fabricated and annealed in argon gas environment in six different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then performed. Based on the verified FEA methodology, several parametric studies are then conducted, including the effects of annealing temperature on Cu protrusion, residual stress distributions of TSV structures. The simulation results are helpful to understand and solve the key problem in TSV fabrication process and reliability challenge.

Study of Annular Copper-Filled TSVs of Sensor and Interposer Chips for 3-D Integration

Actually, the 3-D integrating process is often viewed as the integration of wafer thinning, through-silicon vias (TSVs) etching and filling, redistribution layer formulation, and microbump bonding. The TSV formulation is a critical process because TSV decides the quality of the interconnection. In this paper, the annular copper-filled TSVs are fabricated into the sensor and interposer chips, which are thinned to 100 $\mu \text{m}$ , and 10- $\mu \text{m}$ -diameter TSV is etched and annularly filled by 2- $\mu \text{m}$ -thick copper only utilizing sputtering. It can significantly simplify the chip fabricating process, which only includes the TSV etching (deep reactive-ion etching), insulating layer formation, barrier layer sputtering and copper layer sputtering, and peeling. The thermal reliability of the annularly filled TSV structure is studied by the finite-element simulation, and it is found that the thermal stress is markedly reduced, and in the thermal cycle test, annularly filled TSV samples show better reliability. Meanwhile, the measured electrical conductivity shows a slightly worse but enough electrical conductivity property.

A New Cellular-Based Redundant TSV Structure for Clustered Faults

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process, which greatly reduces the yield of 3-D-ICs. The basic method to repair faulty TSVs (FTSVs) is to transfer the signals on FTSVs through regular TSVs. Many redundant TSV (RTSV) structures have been proposed to repair uniformly distributed FTSVs. For clustering FTSVs, a router-based RTSV structure appears to be a good scheme. But it is not an economical method, since the structure consumes many more hardware resources than normal structures. In this paper, we propose a cellular-based RTSV structure to utilize hardware resources more efficiently for a higher yield. We propose a corresponding algorithm for recovery-route searching. Simulation results show that for 1E6 TSVs and a TSV failure rate of 0.01%, our design consumes only 4.5% more area of all STSVs to achieve a yield above 99.9%. We compare our structure with several other designs and demonstrate the cost-effectiveness of the proposed technique.

Heating Rate Dependence of the Mechanisms of Copper Pumping in Through-Silicon Vias

In three-dimensional stacked-die packages, through-silicon vias (TSVs) are used to connect multiple adjacent dies through solder micro-bumps. During thermal cycling, the thermal expansion mismatch between the copper TSVs and the silicon dies creates large internal stresses in the hetero-structure, resulting in intrusion or protrusion of the TSV relative to the Si die. This phenomenon is commonly known as copper pumping and is a potential reliability concern as it impacts the stability of back-end-of-line structures. In this study, the copper-pumping phenomenon was investigated by thermally loading TSV structures via ex situ and in situ thermal cycling with various heating rates. The resulting TSV protrusion was characterized and it was revealed that copper pumping manifests itself via three distinct mechanisms: plasticity, grain boundary sliding, and interfacial sliding. Electron backscatter diffraction analysis revealed that grain boundary sliding occurs preferentially at incoherent sigma-3 boundaries, while coherent sigma-3 boundaries remain immobile. The operating conditions, including ambient temperature, heating rate and the microstructural features that influence these phenomena are discussed.

Evaluations of heat treatment on polymer adhesive bonding and thermal-induced failure of two-layer through-silicon via structures

In the present study, upper and lower substrates made of p-type Si were bonded using benzocyclobutene (BCB) glue, which was then solidified via rapid thermal annealing at various chamber atmospheres. Inductively coupled plasma was applied to prepare through-silicon via (TSV) holes that penetrated the wafer-BCB-wafer (WBW) composite specimen. SiO2 and Ti films and copper pillars were deposited and filled in sequence to form the WBW TSV structure. These specimens were prepared for thermal tests to determine the earliest failure (fracture) time (Tfailure) for the Ti and SiO2 films and the time required for electrical current breakdown (TBD) in the specimens. Theoretical models, including the Johnson-Cook (J-C) fracture model and a numerical scheme, were developed to predict the Tfailure values for the Ti and SiO2 films. Black’s equation was applied to determine the variations of specimen activation energy with externally applied bottom surface temperature and electrical voltage. The numerical results for (Tfailure)Ti, (Tfailure)SiO2, and TBD are obtained quite close to those from the experiments. The elastic modulus of the solidified BCB material can be increased by fabricating the WBW structure under high vacuums. A relatively lower BCB elastic modulus can lower the maximum strain energy density required for fracture in the SiO2 film of the TSV structure, thus effectively increasing TBD. The rate of effective activation energy is the dominant factor for TBD. The effective activation energy in the preparation of BCB bonding decreases with increasing the vacuum.

Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

In this paper, a high-resistivity silicon (HR-Si) interposer integrated with through-silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5-D/3-D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder-hollow-annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow-annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV’s constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III–V groups’ devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR-Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about −0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and −0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5-D/3-D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.

Insights into Laser Ablation Processes of Heterogeneous Samples: Toward Analysis of Through-Silicon-Vias.

State-of-the-art three-dimensional very large-scale integration (3D-VLSI) relies, among other factors, on the purity of high-aspect-ratio Cu interconnects such as through-silicon-vias (TSVs). Accurate spatial chemical analysis of electroplated TSV structures has been proven to be challenging due to their large aspect ratios and their multimaterial composition (Cu and Si) with distinct physical properties. Here, we demonstrate that these structures can be accurately analyzed by femtosecond (fs) laser beam ablation techniques in combination with ionization mass spectrometry (LIMS). We specifically report on novel preparation approaches for the postablation analysis of craters formed upon TSV depth profiling. The novel TSV sample preparation is based on deep and material-selective reactive-ion etching of the Si matrix surrounding the Cu interconnects thus facilitating systematic focused-ion-beam (FIB) investigations of the high-aspect-ratio TSV structures upon ablation. The particular structure of the TSV analyte combined with the ⌀beam > ⌀Cu-TSV condition allowed for an in-depth investigation of fundamental laser ablation processes, particularly focusing on the redeposition of ablated material at the inner side-walls of the LIMS craters. This phenomenon is of imminent importance for the ultimate quantification in any laser ablation-based depth profiling. In addition, we have developed a new method which allows the unambiguous determination of the crossing-point of the Si/Cu||bare Si interface upon Cu-TSV depth profiling which is based on pronounced, depth-dependent changes in the mass-spectrometric detection of those Si xy+ species formed upon the LIMS depth erosion.