Abstract
The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.
Highlights
With the increasing tendency for the application of miniaturization and high-speed communication, three-dimensional (3D) integrated circuits with through silicon vias (TSVs) have become promising candidates for building modules and systems of high speed, frequency, and density [1,2]
In order to enhance the quantity of transistors in the chips, the vertical stacking of TSVs plays an important role in the field of semiconductor devices, which broke through the bottleneck of traditional two-dimensional integration
Ordinary electroplating cannot achieve a satisfactory effect on full filling due to the so high aspect ratio of TSVs [7]
Summary
With the increasing tendency for the application of miniaturization and high-speed communication, three-dimensional (3D) integrated circuits with through silicon vias (TSVs) have become promising candidates for building modules and systems of high speed, frequency, and density [1,2]. Zhang et al illustrated the whole design and fabrication process of TSVs [4], wherein via filling is a crucial procedure which influences the resistivity and capacity of the electrical parameters, including the reliability of the whole circuit [5]. Ordinary electroplating cannot achieve a satisfactory effect on full filling due to the so high aspect ratio of TSVs [7]. Electroplating for vias was operated with difficulties, such as bonding the TSV wafer to an auxiliary wafer with seed layers [8], pretreating the wafers [9], adjusting the additives in the solution [10], using pulse-reverse current electrodeposition [11], and optimizing the models of simulation [12]. The preconditions for copper deposition with a uniform microstructure have been studied and the type of gelatin additive has been reported [14]
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