Copper filling by electroplating for high aspect ratio TSV

Abstract

3D IC integration based on through silicon vias (TSVs) is expected to provide an alternative technology that can exceed the Moore' Law because of its high packaging density, short signal path, low signal delays. Via filling of conductive materials is regarded as one of the key technologies in the TSV process flow. In this paper, conductive materials such as copper was chosen to fill the TSVs due to its high conductivity, low cost, good compatibility to conventional multilayer interconnections, and relatively good match to silicon's coefficient of thermal expansion. The wafer including blind TSVs that designed with 60 μm in height and 10 μm and 15 μm in diameters was filled copper by electroplating. The microstructure of copper in TSVs was characterized by the scanning electronic microscopy (SEM). Void-free blind TSVs with high aspect ratio up to 6:1 were successfully achieved by bottom-up filling technology.