Investigate the microstructure changes in Cu through-silicon vias (TSVs) under thermal process

Abstract

The through silicon vias (TSVs) technology is one of the key steps to perform the 3D IC integration that can supply short vertical interconnects and high I/O counts. Copper (Cu) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. The copper filling in the TSV is completed by the electroplating and the annealing will be performed to eliminate the residual stress in TSV and to improve the metallurgy of filled copper. The TSV reliability is much relied on the metallurgy and basic material properties of copper in the TSV. During thermal conditions, e.g. testing or usage, the metallurgy and material properties changes should be well understood. In this paper, the chip with blind TSV that was filled copper was fabricated first. Then the sample was submitted to annealing under 410°C for 15 and 30 minutes. The microstructure of copper in TSV was characterized by the focused ion beam (FIB) and scanning electronic microscopy (SEM). The results revealed the grain size and distribution affect by annealing process. The defects in the TSV after annealing was observed and discussed.