High Aspect Ratio through Silicon Via Filling By Nickel-Tungsten Alloy Using Graphene As a Conducting and Barrier Layer

Abstract

Recently, three-dimensional (3D) chip stacking becomes more and more important because of “More than Moore” story. Through silicon via (TSV) technology is one approach to achieve the target of “more than Moore”. However, the coefficient of thermal expansion (CTE) of copper filled in the TSV may lead to failure of the TSV interconnects because the copper CTE is much higher than that of silicon. The packaging materials with different CTEs will induce large stress at interfaces of materials. To overcome this problem, we choose nickel to substitute copper as a filling material of TSV since the nickel CTE is lower than copper CTE. To further decrease the CTE of the filling material, a few tungsten whose CTE is similar to that of silicon is codeposited during filling plating. Graphene has drawn extensive attention due to its outstanding electrical and thermal properties. In addition, graphene can be used as a barrier layer of copper diffusion. Also, the CTE of graphene is similar to that of silicon. Hence, we use graphene to replace the TiN barrier layer and the copper seed layer, which was used in the traditional TSV process. The filling performance is evaluated by examining vertical cross-sections and top-down cross-section of the filled TSVs by using optical microscope (OM). The Ni-W pillar is examined by scanning electron microscopy (SEM). The thermal reliability of the fully filled TSV is evaluated after a thermal annealing process. The CTE of the filled Ni-W is measured by thermomechanical analysis.