Stress evolution mechanism and thermo-mechanical reliability analysis of copper-filled TSV interposer

Yuan Chen,Wei Su,Si Chen,Hong-Zhong Huang,Ping Lai,Xiao-Ling Lin

doi:10.17531/ein.2020.4.14

Abstract

Through silicon via (TSV) has become one of the key emerging trends of three-dimensional (3D) packages, as it can realize vertically interconnect between stacked-dies. Due to large mismatch in thermal expansion coefficients (CTE) between the copper via and the silicon, significant mechanical stresses are induced at the interfaces when TSV structure is subjected to thermal stresses, which would greatly affect the reliability and electrical performance of TSV 3D device. In this paper, the relationship between the state of stresses and failure of TSV had been explored by combining finite element model simulation (FEM) and failure physical analysis. The position of the maximum stress of the TSV structure was obtained by FEM analysis. The relationship of stress and displacement change with temperature was also studied. And a thermal cycling experiment was conducted to validate the simulation results. Physical failure analysis after thermal cycling experiment was used to verify the degradation mechanism predicted by thermo-mechanical simulation.

Highlights

With the development of three-dimensional (3D) integrated packaging [3, 5], Through Silicon Via (TSV) has become one of the most promising technologies in realizing 3D stacking package[1, 21]
The Mises stress distribution cloud diagram of the TSV interposer indicates that under thermal stress, uneven stress and strain appear in the TSV structure, which is analyzed by the elastoplastic yield criduring temperature maintenance period
As temperatures rising, in the X-direction both sides of TSV displaced towards the middle and the maximum displacement value appeared at the center of both sides

Summary

Introduction

With the development of three-dimensional (3D) integrated packaging [3, 5], Through Silicon Via (TSV) has become one of the most promising technologies in realizing 3D stacking package[1, 21]. Advanced TSV technology can realize 3D heterogeneous integration[28], high speed, wide band, small size and high performance through vias and micro-bumps. TSV is an important physical and electrical connection between chips [19], and the reliability of TSVs affects considerably on the reliability of 3D integrated devices [18]. TSV technology faces many difficulties and challenges in processing [12, 16]. Its reliability has not been fully understood [15]. It is of paramount significance to investigate stress evolution mechanism and thermo-mechanical reliability of copper-filled TSV

Results

Discussion

Conclusion