Low-loss through silicon Vias (TSVs) and transmission lines for 3D optoelectronic integration

Abstract

The optoelectronic hybrid integration based on co-package has attracted much attention to meet the requirements of high-performance chip development and functional integration. TSVs and redistribution layers (RDLs) are of great importance for both the packaging process and the system design of 3D integration. This paper presents the measurements and analysis of TSV and RDL test structures, from DC to high frequency up to 67 GHz. TSVs and RDLs with low insertion loss up to 67 GHz are demonstrated and the impact of TSV arrangements on the transmission performance are analysed. The insertion loss of a 500 μm long coplanar waveguide (CPW) transmission line of frontside RDL (FSRDL) is 0.75 dB at 67 GHz. The insertion loss is less than 1 dB at 67 GHz for a TSV-RDL signal path with the length of 500 μm.