A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs

Abstract

Through Silicon Vias (TSVs) are crucial elements for the reliable operation and yield of three dimensional integrated circuits (3D ICs). Defects are a serious concern in TSV structures. A post-bond, parallel testing and diagnosis scheme is proposed in this work, for the detection and location of resistive open or short to substrate defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing method provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical model simulations and Monte-Carlo analysis results, using the 65 nm technology of TSMC, prove the effectiveness of the new method. Additionally, two representative methods from the literature are simulated and compared to the proposed one, in terms of effectiveness, robustness, tolerance, cost and design for testability effort. The proposed scheme is proven to perform better based on all presented criteria.