Abstract
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing scheme provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical simulations and Monte-Carlo analysis results, using the 65nm technology of TSMC, accentuate the effectiveness of the new method.
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