Thermal–Mechanical Performance Analysis and Structure Optimization of the TSV in 3-D IC

Abstract

The through-silicon via (TSV) technology is widely used in 3-D integrated circuit (3-D IC) devices. However, the TSV could cause great thermal stress due to the mismatch of the thermal expansion between different materials, which affects the performance of the 3-D IC. In this work, a finite element model of the 3-D IC device with both internal pin-fin microchannels and all-copper interconnection is established. A substructure model is further developed and validated against the results obtained from the full model. Then, the thermal-mechanical performances of the TSV structure under thermal cycling loads are investigated based on the substructure model. The results show that the maximum stress locates at the edge of the interface between TSV_copper and memory, and the deformation on the TSV_copper-memory interface is dominated by shearing, which may cause the debonding of the interface. Moreover, the influences of the TSV structure parameters on the maximum thermal stress and TSV_copper's electrical resistance are analyzed. Then, the TSV structure is further optimized to reduce the stress and improve the electrical conductivity. Compared with the original design, the maximum von Mises stress and TSV_copper resistance of the optimized structure can be reduced by 18.4% and 40.6%, respectively.