Through Silicon Via Interposer Research Articles

Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV Interposers

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV) interposers will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV interposer. Also, some recommendations will be provided.

Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme

In this article, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into the logic layer of the high bandwidth memory (HBM) to expose an excess dynamic random access memory (DRAM) bandwidth. With parallelized DRAM architecture and a high-speed through-silicon via (TSV) structure, the proposed scheme successfully extends the DRAM bandwidth of processing-in-memory (PIM). Also, the total energy consumption is decreased by the reduced interconnection and capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility for application to the current HBM. The logic layer and DRAM layers in the HBM are configured to embed the processing units and parallelize the DRAM channels. For high-speed data transfer with low interconnect energy, the TSV and silicon interposer channels are designed and analyzed in consideration of signal integrity (SI). Based on the physical design, we obtained the interconnect length in detail. The interconnect energy and delay of the silicon interposer and on-chip interconnect were modeled through a SPICE simulation. We analyzed the accurate effects of interconnect reduction caused by PIM. For overall system performance and efficiency analysis, a cycle-level architectural simulation was conducted. We successfully evaluated and analyzed the system performance for memory-intensive applications. As a result, the proposed PIM-HBM achieves 53% and 10.4% improvement on average in computing performance and energy efficiency compared to the conventional graphic processing unit of high bandwidth memory (GPU-HBM).

Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

Signal integrity in high density through silicon via (TSV) has become a key concern in 3D integrated circuits design as its continuous scaling down. In this paper, the corner/edge effect of TSV arrays is proven to be non-neglectable and is characterized by coupling capacitance, mutual inductance, S parameter, and maximum noise respectively. The 6C static shielding method (X. Cui et al., ICEPT, 2018, p. 944) is improved by inserting ground TSVs at the array corners according to our evaluation. At last, we proposed three layout optimization rules for TSV interposer design to generate a more balanced electromagnetic shielding and to achieve better signal integrity.

A RF Redundant TSV Interconnection for High Resistance Si Interposer.

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

Stress evolution mechanism and thermo-mechanical reliability analysis of copper-filled TSV interposer

Through silicon via (TSV) has become one of the key emerging trends of three-dimensional (3D) packages, as it can realize vertically interconnect between stacked-dies. Due to large mismatch in thermal expansion coefficients (CTE) between the copper via and the silicon, significant mechanical stresses are induced at the interfaces when TSV structure is subjected to thermal stresses, which would greatly affect the reliability and electrical performance of TSV 3D device. In this paper, the relationship between the state of stresses and failure of TSV had been explored by combining finite element model simulation (FEM) and failure physical analysis. The position of the maximum stress of the TSV structure was obtained by FEM analysis. The relationship of stress and displacement change with temperature was also studied. And a thermal cycling experiment was conducted to validate the simulation results. Physical failure analysis after thermal cycling experiment was used to verify the degradation mechanism predicted by thermo-mechanical simulation.

Modeling simplification for thermal mechanical stress analysis of TSV interposer stack

The generalized plane deformation (GPD) mode is a simplified model that effectively reflects the information of whole chip and local regions. In this paper, we propose a modified-GPD model for thermal-stress analysis of through silicon via (TSV) interposer application. Highly doped poly silicon is used to fill TSV in our modeling. The boundary conditions are optimized. The accuracy is largely improved and the computation time is reduced compared with conventional GPD model.

Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

In this paper, a high-resistivity silicon (HR-Si) interposer integrated with through-silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5-D/3-D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder-hollow-annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow-annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV’s constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III–V groups’ devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR-Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about −0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and −0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5-D/3-D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.

High-Resolution E-Jet Enhanced MEMS Packaging

High-resolution electrohydrodynamic inkjet printing has potential to simplify the existing MEMS package fabrication through its additive and digital properties without sacrifices in the I/O density of the package. Initially, the replacement of certain lithographic process steps would lead to decreased material consumption and increased cost-effectiveness of the package fabrication; in long term, the large-scale adoption of additive process steps would enable increasing device customizability and lead to cost-effective fabrication of small batches and even fully tailored device specific MEMS packages. In our work, we have demonstrated the feasibility of this approach by replacing selected lithographic process steps by using high-resolution inkjet technology (Super Inkjet, SIJ Tech.) for metallization of high-density redistribution layers (RDL), metallization of through-silicon-vias (TSV) and fabrication of under bump metallization (UBM). Fully printed high-density redistribution layer (RDL) A fully printed high density RDL in two metallization layers was demonstrated with a combination of Super Inkjet (SIJ) and conventional inkjet printing (DMP-2831). The SIJ was used for the metallization of 5/5 µm W/S high-density circuitry in MET1 and MET2 and DMP for the dielectric layer separating the metallization layers. In order to achieve low resistance conductors with minimal footprint, multilayer printing was employed resulting in a high aspect ratio of over one. The MET1 to MET2 microvia was also additively fabricated by first printing a narrow ~10µm pillar in MET1 with SIJ, then surrounding the pillar with DMP printed dielectric layer and finally connecting the top of the pillar with SIJ printed MET2 conductors. [1] A fully printed RDL increases the customizability of the package fabrication process to a level where each individual interposer on wafer could be fitted with customized RDL to accommodate a specific MEMS device. In addition, the material consumption is reduced significantly since the fully printed RDL does away with global deposition of metal, masking and etching required in standard lithography based metallization. It is also important to notice that these advantages are achieved without sacrificing the density the RDL: the 5/5µm width and spacing for conductors and 10µm microvia diameter are similar to what is achieved with current lithographic processes. Additive metallization of high-density through-silicon-vias (TSV) The sub-femtoliter droplet size of the SIJ and concomitant fast evaporation rate was utilized in rapid metallization of high-density TSVs with top diameter of 23µm and spacing of 10µm. In standard practice CVD, PVD, electroplating or electroless deposition are utilized for metallization of high density TSVs leading to long process time and low level of customizability. The conventional inkjet printing could be used for over 50µm TSV diameters, but it is difficult to achieve stable operation with a 1pl cartridge which could produce small diameter droplets for filling the high density TSVs of 20µm diameter; also the low evaporation rate of the relatively large droplets would prolong the process time since evaporation step would need to be included in the process; in addition, the positioning accuracy of the conventional inkjet printer (e.g. DMP) might not be sufficient for this application. In this regard it was noticed that the SIJ printing has many advantages: first, the sub-femtoliter droplet size leads to fast evaporation rate enabling the metallization of the vias at room temperature without substrate heating or evaporation steps; second, the positioning accuracy of the SIJ stage is under 1µm enabling accurate deposition of the ink in to the TSV; third, since most of the solvent in the droplets is already evaporated during the flight, the chances for creating gas pockets in the filling are reduced. [2] High-resolution inkjet printing for creating smooth UBM The previously discussed approaches for utilizing the high-resolution Super Inkjet printing were restricted to features inside the interposer. However, this fabrication technology also finds utility on the outside of the package, which does not necessarily need such high-density features, but where low surface roughness is important. Highlighting this advantage, a smooth under bump metallization has been fabricated with SIJ on top of a large diameter partially metallized TSV; the TSV has been filled with SIJ printed polymer dielectric. [3] References Laurila et al, “Combination of E-jet and inkjet printing in additive fabrication of multilayer high-density RDL of silicon interposer”, IEEE Trans. Electr. Dev., vol. 64, no. 3, pp. 1217-1224, March 2017 Khorramdel et al, “Metallization of high-density TSVs using Super Inkjet technology”, 2015 IEEE 65th ECTC conf., San Diego, 2015, pp. 41-45 Khorramdel et al, “Inkjet printing technology for increasing the I/O density of 3D TSV interposers”, Microsystems & Nanoengineering, vol. 3, 17002, Apr. 2017

Inkjet printing technology for increasing the I/O density of 3D TSV interposers

Interposers with through-silicon vias (TSVs) play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems. In the current practice of fabricating interposers, solder balls are placed next to the vias; however, this approach requires a large foot print for the input/output (I/O) connections. Therefore, in this study, we investigate the possibility of placing the solder balls directly on top of the vias, thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections. To reach this goal, inkjet printing (that is, piezo and super inkjet) was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer. The under bump metallization (UBM) pads were also successfully printed with inkjet technology on top of the polymer-filled vias, using either Ag or Au inks. The reliability of the TSV interposers was investigated by a temperature cycling stress test (−40 °C to +125 °C). The stress test showed no impact on DC resistance of the TSVs; however, shrinkage and delamination of the polymer was observed, along with some micro-cracks in the UBM pads. For proof of concept, SnAgCu-based solder balls were jetted on the UBM pads.

Prediction of deformation during manufacturing processes of silicon interposer package with TSVs

The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature (Tg) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2μm line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Induced thermo-mechanical reliability of copper-filled TSV interposer by transient selective annealing technology

Managing the stability of related processes in the integrated manufacturing of three-dimensional integrated circuits (3D-ICs) remains unresolved, especially with regard to the thermo-mechanical behavior of copper filled through silicon via (TSV) interposer during annealing. In this work, transient annealing is successfully applied on the filled copper using only one form of selective heating technology. To address the integration problem, transient thermo-structural coupling analysis using a nonlinear finite element simulation is proposed. Compared with the experimental data, the proposed simulation is found to be highly reliable. Analytical results show that temperature decreases from the top surface of the TSV to other regions within a silicon-based TSV interposer. Stress-induced fracture is common among bonded films, thereby worsening the subsequent mechanical reliability of 3D-IC devices. Moreover, the extent of keep-out zone induced by residual stress of Cu-filled TSV is also defined through the simulation-based mobility gain of nano-scaled devices. In accordance with the results of this investigation, an improvement can be obtained by optimizing the fabrication parameters during annealing. The proposed technology provides a high throughput and reliable processes in TSV manufacturing.

Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization

Nowadays, Through Silicon Vias (TSV) with High Aspect Ratio (HAR > 8:1) are seriously mandatory in the 3D Integrated Circuits in order to maintain semiconductor performance trends into new technological advances. Consequently, successful integration of HAR TSVs requires solving key challenges in terms of technical (layer continuity, step coverage, adhesion) and industrial (scale-up to 300mm diameter wafer) developments. In this paper, one proposes to discuss those questions by means of the integration of an electrografting (eG) seed layer on a high conformal, but low conductive MOCVD TiN copper diffusion barrier. On the one hand, one studies the impact of different electrochemical parameters on eG Seed layer properties. On the other one, the encountered difficulties are presented and solutions are proposed to integrate eG Seed layer at a large scale i.e. on a specific industrial 300mm diameter wafer plating chamber.

Effects of silicon via profile on passivation and metallization in TSV interposers for 2.5D integration

In this paper, the influences of profile factors on passivation and metallization in deep vias of Through Silicon Vias (TSV) interposer, such as taper angle, scallops and aspect ratio (AR), were investigated for 2.5D integration. The diameter of vias was scaled from 40μm to 100μm. Conventional Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition and Physical Vapor Deposition (PVD) metallization processes were used. Slightly tapered vias was formed by Bosch process combination with isotropic etching. This investigation shows that the SiO2 passivation of the TSV vias with PECVD deposition is completely insensitive to the factors related to via profile. But the metallization with sputtering is quite sensitive to taper angle, scallops and AR. A good trade-off between passivation and metallization can be realized to fabricate the TSV interposer by controlling the taper angle in the range of 1–3°. The TSV vias with scalloping pattern is difficult to achieve the continuous and conductive metal layer. The continuous metal layer can be successfully achieved to realize the conductive interconnection with front-side multi-level metallization (MLM) layers in a maximal AR of ∼3 for tapered vias.

Advanced Silicon Interposer for High density and High Integration Electronic Packages

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

Quartz resonator assembling with TSV interposer using polymer sealing or metal bonding.

This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resonator using ceramic-based package. With evaluation of mechanical structure design and package performances, this quartz resonator with advanced silicon-based package shows great manufacturability and excellent performance to replace traditional metal lid with ceramic-based interposer fabrication approach.

Comparison of Fabrication Process Capability and Electrical Performance with Silicon and Glass Interposers

As electronic product becomes smaller and lighter with an increasing number of function ↚ the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of TSV interposers and TGV interposers with fine pitch high aspect ratio through vias.

3D Wafer Level Heterogeneous Integration

3D integration is worldwide considered as one of the most important key technology for microelectronics to meet the growing demands regarding more functionality with concurrent increase in performance as well as miniaturization and cost reduction. So 3D integration is of main relevance for application areas e.g. cyber physical systems, internet of things, ambient assisted living (AAL) as well as information & communication, logistics, security, automotive, health care and industrial electronics. Besides following “More Moore”, Europe is pursuing a strategy on heterogeneous integration approaches following “More than Moore”. In this context, individual and different 3D integration approaches are adapted to the specific application scenarios.Interposers with Through Silicon Vias (TSV) are becoming a very important element for the realization of 3D System in Packages (SiPs). Main advantages of silicon interposers are the decoupling of front end/back end processing for the implementation of TSVs, redistribution layers (RDL) and the integration of active and passive devices. Besides independent manufacturing, interposers can be realized in short time-to-market time frame and in a cost effective way. TSV interposers are designed and manufactured for the different application areas which results also in different technical specifications ranging from high density TSV integration and high density RDL for digital applications to interposers for RF application as well as MEMS integration and optical interconnects.The presentation will highlight results and technical achievements for 3D integration using TSV interposer and addresses as well the broad spectrum of topics from design, technology and reliability related to 3D systems.Concerning technical features, interposers deal with high density wiring redistribution layers (RDL), TSVs and top/bottom side interconnect formation (bumping). This allows the electrical signal routing across the top side and to the interposer back side. Some new applications appear to require up to 4 layers RDL of less than 1μm line/space and silicon oxide/nitride dielectric layer.Silicon interposers with TSVs provide additional features to address 3D-SiP for heterogeneous integration. These include:Device carrier for stacked devices,High density wiring between (stacked) components,3D device stacking using TSVs,Integrated passive devicesEmbedding of active devices into the IP,Functional layer integration (actors, sensors, antennas),Modularization,Integrated test features For the assembly and 3D stack formation of the devices, different interconnection technologies, e.g. micro solder bumps (SnAg) and copper pillars, are used to deal especially with surface topography of the devices and warpage of the board/substrate.Beside silicon interposer, also glass interposers are emerging elements for specific applications. Compared to silicon interposers, glass interposer currently have only limited via dimension and cannot deal with high density TSVs, e.g. <5µm diameter and 10µm pitch. For this, the supply chain is still emerging. The metallization process for silicon interposers is commonly established in wafer fabs. However, most of these facilities do not possess via-last or bumping capability. SUMMARY 3D integration technology is one of the main drivers in packaging and system integration to meet the requirements for high functionality, highly miniaturized smart systems.Future advanced 3D systems will result in complex 3D stacking approaches using the TSV technology. Silicon interposers with TSVs are an important element to combine different advanced devices into one miniaturized system (SiP) with high functionality and to overcome currently existing issues regarding TSV integration into active devices. One important task is the supply chain between e.g. IDMs, OSAT or packing houses.Another crucial aspect is the balance between performance improvement and 3D manufacturing cost (TSV & packaging). So the implementation of 3D integration using TSV and interposer is very product specific. 3D integration requires, beside the technology approaches, also an overall SiP process integration approach which addresses design, technology and reliability.Fraunhofer IZM’s center “All Silicon System Integration Dresden - ASSID” and the Fraunhofer Cluster 3D Integration (http://www.3d-integration.fraunhofer.de/en.html) are focusing on the development and prototyping of 3D systems using Cu-TSVs in active devices (via middle, via last) and silicon interposers as well.

Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization

After many years of developments, 3D Integrated Circuits have emerged as a potential key enabler for maintaining semiconductor performance trends. Through Silicon Vias (TSVs) sit at the foundation of the 3D-IC revolution for extending semiconductor integration into a new phase. Integrated device manufacturers and fabless design houses need small, high-density, fine-pitch vias for improving signal integrity and Si real-estate savings, without possibility to wait for very thin wafer processing and handling technologies to become a mainstream. Deep TSVs with Aspect Ratio (AR) greater than 10:1 elegantly fulfill those requirements. But they cannot be manufactured with acceptable yield/cost using traditional dry processes for liner, barrier and seed deposition. Conventional dry techniques show basic shortcomings and impose high capital investments. Beyond that, physical limitations of directional dry techniques prevent the deposited layer from reaching good step coverage or even continuity inside the vias, which is required to perform void-free gap filling with electroplated copper.To overcome those limitations, alternative wet solutions based on electrografting (eG) and chemical grafting (cG) technologies were developed. These latter are two fundamental molecular engineering technologies, delivering high-quality films (continuous, adherent and uniform) for high aspect ratio (HAR) TSVs. This paper will focus on the integration of eG copper seed as a mature solution for TSVs with HAR, to overcome PVD Copper limitations in those dimensions.Electrografting is based on surface chemistry formulations and processes. It is applied to conductive and semi-conductive surfaces, and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. Contrary to electro-deposition which requires a potential supply throughout deposition to fuel the redox processes, electrografting is an electro-initiated process which requires a charged electrode only for the grafting step, but not for the thickening. As eG is mainly a cathodic process, it can generally be applied to various metallic and semiconducting surfaces without any concern over oxide formation. In a first approach, electrografting was used for polymer deposition on various conductive and semi conductive substrates. In this case, the grafting occurs via a direct electron transfer from the cathode to the electro-active monomers in solution (Figure 1). Mechanisms of radical polymerization show that polymer electrografting is an electro-induced grafting process followed by a purely chemical propagation step (polymerization). The first electro-induced step is crucial to form the chemical bond between the polymer and the surface. A specific organic precursor (B) is used both to form a first primer grafted layer and to initiate the polymerization of the vinyl monomer (A) in solution. The termination step of the polymerization leads to the grafting of macromolecular chains (-[A-A-A]n-B) onto the first primer grafted layer. Based on the polymer electrografting concept, formulation and processes have been developed to graft metal layers onto various type of conductive and semi-conductive surfaces. In opposite, for instance, to copper electrodeposition which has to be performed on conductive layer to avoid terminal effect induced by resistive copper diffusion barrier layers, copper electrografting technology can interestingly be achieved on highly resistive substrates.A bath containing specific organics and copper has previously been developed to deposit the Cu seed layer. It has been shown that electrografted copper seed can directly be applied to various dry-deposited diffusion barriers (Ta, TaN, Ti, TiN, TiW) without any adhesion promoter in between.This paper deals with the integration of eG Seed layer on a conformal MoCVD TiN copper diffusion barrier on 8:1 aspect ratio TSVs. First, detailed mechanism of the electrografting process will be discussed. Secondly, the influence of the electrical barrier resistivity (PVD TiN, Ni vs MoCVD TiN) on the plating properties into the via will be presented for both experiments done at coupon level and up scaled in an industrial 300mm diameter wafer reactor. Plating differences will be considered in term of growth initiation and step coverage for these two experimental configurations. Fine tuning of the process parameters at the 300mm scale will then be examined to achieve a conformal, uniform and adherent copper seed layer in order to successfully respond to the high AR copper filling challenge in the TSV applications. Finally, void-free filling, integration in a conventional 3D process flow and electrical characterizations on high aspect ratio TSV middle daisy chains are ongoing. As a perspective to decrease the cost of TSV metallization, the entire wet metallization process flow including isolation, copper diffusion barrier, copper seed and copper fill steps will be developed at the end of this paper.