Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

Abstract

Signal integrity in high density through silicon via (TSV) has become a key concern in 3D integrated circuits design as its continuous scaling down. In this paper, the corner/edge effect of TSV arrays is proven to be non-neglectable and is characterized by coupling capacitance, mutual inductance, S parameter, and maximum noise respectively. The 6C static shielding method (X. Cui et al., ICEPT, 2018, p. 944) is improved by inserting ground TSVs at the array corners according to our evaluation. At last, we proposed three layout optimization rules for TSV interposer design to generate a more balanced electromagnetic shielding and to achieve better signal integrity.