Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization

Abstract

Nowadays, Through Silicon Vias (TSV) with High Aspect Ratio (HAR > 8:1) are seriously mandatory in the 3D Integrated Circuits in order to maintain semiconductor performance trends into new technological advances. Consequently, successful integration of HAR TSVs requires solving key challenges in terms of technical (layer continuity, step coverage, adhesion) and industrial (scale-up to 300mm diameter wafer) developments. In this paper, one proposes to discuss those questions by means of the integration of an electrografting (eG) seed layer on a high conformal, but low conductive MOCVD TiN copper diffusion barrier. On the one hand, one studies the impact of different electrochemical parameters on eG Seed layer properties. On the other one, the encountered difficulties are presented and solutions are proposed to integrate eG Seed layer at a large scale i.e. on a specific industrial 300mm diameter wafer plating chamber.