Through Silicon Via Formation Research Articles

E-field induced keep-out zone determination method of through-silicon vias for 3-D ICs

An increase in the number of the through‑silicon vias (TSVs) per unit area causes the electrical channel in neighboring semiconductor devices to be closer to the depletion region induced by the electric-field (E-field) around the TSV. A keep-out zone (KOZ) is required to ensure the proper operation of three-dimensional integrated circuits (3-D ICs) using TSVs given these negative effects. The proposed method with which to determine the KOZ for 3-D ICs includes procedures for extracting the charges produced during the TSV formation process and for calculating the depletion region from a nonlinear metal-oxide-semiconductor (MOS) capacitance model. The results of a comparison of the proposed method with a previous method show that the charge carriers in the depletion region and charge-type imperfections of in TSV must be considered for an accurate KOZ.

Advanced through silicon vias for hybrid pixel detector modules

The through-silicon via (TSV) technology offers high-density vertical stacking of integrated circuits, providing a smaller and simpler structure, whilst increasing connectivity and performance. In High-Energy Physics (HEP) experiments, via-last TSVs are exploited to build low material modules for the upgrades of pixel detectors at the High Luminosity LHC (HL-LHC). In order to prove this concept a versatile via-last TSV process is being developed using ATLAS FE-I4 pixel read-out wafers. It allows modules being operated from the chip backside using the TSV-enabled connectivity. The current status of this development is discussed and results of the TSV formation process and the fabrication of the redistribution layer (RDL) on the ATLAS FE-I4 wafers are shown together with electrical results of the first read-out chips while operated via TSVs and RDLs. Another emphasis of this R&D is the industrial benefit, especially for small and medium companies, which will have access to more affordable and, therefore, competitive option.

Study on Ag/Sn multilayer thin film bonding for 3D stacked semiconductor

Through-silicon via (TSV) technology for 3D stacking is attracting much attention as a means of alleviating the miniaturization limits on advanced semiconductor devices. Despite a great deal of research, low load (<1 MPa), low temperature (<473 K) and short time (<300 s) solid phase bonding with high heat resistance (>623 K) to prevent the damage of weak low-k dielectric material, etc. has not been realized. In this work, we examine a new Ag–Sn thin film bonding system to replace Cu–Cu direct bonding. It is found that Ag/Sn/nano Ag-nano Ag/Sn/Ag thin film bonding systems (especially when the film thickness of the surface Ag is controlled to around 10 nm) is a promising approach because (1) it enables low load (<0.4 MPa), low temperature (<453 K) and short time (<300 s) bonding, and (2) the bonded interface has a high heat resistance (>673 K) and joint strength (>29 MPa). It is found that it may be possible to realize an optimal solid-phase bonding system for wafer-level 3D-stacking for 3D-IC which can satisfy a hierarchical temperature-based bonding method that includes TSV formation.

Si Etching for TSV Formation

Through silicon via (TSV) technology is being considered as a promising technology in three-dimensional packaging, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. The Bosch process is the most widely utilized DRIE process for producing high-aspect ratio TSVs. The primary steps in the Bosch process are silicon isotropic etching and wall passivation in sequential cycles. SF6 is used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. Controlling the scallop is key good insulation and metal coverage. In this study, TSVs with scallops smaller than 100nm was obtained by adjusting the flow ratio of SF6 to C4F8 and the cycle time ratio between SF6 and C4F8. Unfortunately this combination leads to the formation of silicon grass at the bottom of the TSV. The addition of O2 during the SF6 etch cycle was found to eliminate the occurrence of Si grass. Finally, TSVs with low scallop were consistently obtained without Si grass by using SF6/O2 during the etch cycle and C4F8 during the passivation cycle.

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

A reliable Cu–Sn stack bonding technology for 3D-TSV packaging

In this paper, Cu–Sn stack bonding technology for 3D-TSV packaging was described; some key technologies such as TSV (through silicon via) formation, silicon wafer thinning, TSV electroplating and Cu–Sn multilayer stack bonding were introduced. First of all, some sample chips with TSV and Cu–Sn bonding pads were fabricated for stacking. Then, two kinds of stack bonding experiments with or without TSV were carried out, respectively. 3-die, 7-die, and 10-die stacks were bonded and assembled. Finally, the bonding strengths of 3D-TSV stacking were characterized by shear test and tensile test, and also the electrical properties, thermal properties and corrosion resistance of stacked module. All the test results suggested that the reliable stack bonding technology can be used for 3D integration applications.

Next Generation Electrochemical Deposition TSV Fill

The first generation of through silicon via (TSV) designs for interposer and 3D die stacking has concentrated on TSV features with aspect ratio (AR) on the order of ten. Typical via sizes are 10 X 100 um for interposer and 5 X 50 um for 3D applications. Ionized physical vapor deposition (IPVD) has been successful in depositing barrier and seed layers in these AR=10 vias that allow efficient “bottom-up” filling by electrochemical deposition (ECD) using available chemistries. While these applications are currently moving to pilot lines and low scale production, research and development has already begun on the next generation of TSV structures for interposer and die stacking. These may be based on via middle or via last designs. They are expected to increase in aspect ratio for denser TSV arrays while maintaining similar wafer thickness. Structures with AR in the range of 15–20 are being designed and produced. For interposer, a typical structure might be 8 X 120 um and 2 X 40 um for 3D stacks. These structures will challenge all TSV formation processes, including etch, dielectric liner deposition, barrier-seed deposition and TSV fill. This paper will focus on barrier-seed and TSV fill processes. IPVD barrier-seed deposition will be difficult for AR~15–20 and will require much longer deposition times for complete via coverage. Long IPVD times will produce thick overburden and pinch off the opening at the top of vias. Even if successful, IPVD may not be viable economically. More conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) and wet processes, like electro-less plating and conformal ECD, may be better alternatives to IPVD. A conformal process only needs to deposit the minimum required seed thickness in the via for successful ECD filling with the overburden being nearly the same thickness. The development of a successful conformal barrier-seed process may even challenge IPVD for AR=10. This paper presents ECD TSV fill results using several conformal barrier-seed processes, demonstrating the feasibility of this approach for structures with AR = 10–20.

次世代三次元積層半導体用 Ag/Sn系多層薄膜電極間接合に関する研究

Through-silicon via (TSV) technology for 3D stacking is attracting much attention as a means of alleviating the miniaturization limits on advanced semiconductor devices. Despite a great deal of research, low load (<1 MPa), low temperature (<473 K) and short time (<300 s) solid phase bonding with high heat resistance (>623 K) to prevent the damage of weak low-k dielectric material etc. has not been realized. In this work, we examine a new Ag-Sn thin film bonding system to replace Cu-Cu direct bonding. It is found that Ag/Sn/nano Ag-nano Ag/Sn/Ag thin film bonding systems (especially when the film thickness of the surface Ag is controlled to around 10nm) is a promising approach because 1) it enables low load (<0.4 MPa), low temperature (<453 K) and short time (<300 s) bonding, and 2) the bonded interface has a high heat resistance (>673 K) and joint strength (>29 MPa). It is found that it may be possible to realize an optimal solid phase bonding system for wafer-level 3D-stacking for 3D-IC which can satisfy a hierarchical temperature based bonding method that include TSV formation.

Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme

A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.

Micromachined stress-free TSV hole for AlGaN/GaN-on-Si (1 1 1) platform-based devices

This paper presents a micromachined stress-free through silicon via (TSV) backend process for AlGaN/GaN-on-Si (1 1 1) platform-based devices, which was processed by assisted back grinding, chemical mechanical polishing, deep reactive ion etching (DRIE) and copper (Cu) electroplating for the TSV. The metal-filled TSV structure was formed to enhance thermal conduction from the frontend terminal to the backend terminal, especially the source region of the AlGaN/GaN-on-Si (1 1 1) platform-based RF power devices. At the end of a stress-free TSV dry etching process, we have changed RF power 600 W to 300 W to minimize thermal stress of the fabricated TSV electrode pad structure of the AlGaN/GaN-on-Si platform-based devices. Additionally, we have sputtered a multi-metal layer and electroplated Cu metal to interconnect a topside electrode to TSV. To protect the thinned TSV electrode pad structure from water pressure in a sawing process, we have covered photoresist (AZ4330RS) of 3.3 µm thickness on the top area of the structures. We confirmed that the proposed TSV formation method assisted by low-power operation DRIE and protection of the thinned TSV surface by using the thick photoresist is very effective to create minimally stressed TSV structures in AlGaN/GaN-on-Si platform-based devices. The improvement was proved by the yield of dice without bursting the pad structures on a 4 inch AlGaN/GaN-on-Si wafer.

Copper seed layer repair using an electroplating process for through silicon via metallization

Through silicon via (TSV) is a key technology for three-dimensional chip stacking, which serves as a bridge to connect multiple devices in the z-direction. Void-free copper deposition in a TSV is essential for reliable TSV fabrication. Deep reactive ion etching (DRIE) process (i.e., the Bosch process) has been widely used for deep TSV formation because of its high aspect-ratio etching capability. However, the sidewall of a TSV is not flat after the DRIE process, which frequently results in a so-called ''scallop'' structure on the sidewall. After a copper seed layer is deposited on the TSV sidewall by sputtering, the step coverage of the copper seed layer is poor, especially at a high aspect ratio. To solve this problem, we use a copper electroplating process to repair the discontinuous seed layer caused by the ''scallop'' structure. The seed layer repair formula that contains a polymer additive allows the growth of an electroplated copper seed layer to be faster in the horizontal direction (parallel to the sidewall surface) than in the vertical direction (normal to the sidewall). The polymer additive is a crosslinked polyamide that bears organic functional groups of R1?NH2 and R2?CO?NH?R3, which prefers to stay on the terraces of copper crystals to inhibit the vertical copper deposition and correspondingly facilitate the horizontal copper deposition. After the repair plating process, the discontinuous seed layer becomes continuous, so that TSVs with diameters of [email protected], which originally failed to achieve copper superfilling, are fully filled by means of copper electroplating.

Reliability of key technologies in 3D integration

3D IC packaging offers miniaturization, high performance, low power dissipation, high density and heterogeneous integration. Through-silicon via (TSV) and bonding technologies are the key technologies of 3D IC, and the corresponding reliability has to be well evaluated and qualified before real production applications. This paper reviews the emerging 3D interconnection technologies in worldwide 3D integration platforms with the latest reliability assessment results, including the reliability demonstration of Cu and oxide hybrid bonding in Ziptronix’s platform, micro-bump and adhesive hybrid bonding in ITRI’s platform, adhesive bonding followed by TSV formation in WOW alliance’s platform, wide I/O interface TSV interposer in Xilinx’s platform, and the active and passive TSV interposer in Samsung, TSMC and ASE’s platforms. With low temperature bonding and TSV processes, optimized design and material selection to lower the induced stress and warpage, these platforms are successfully developed with enhanced reliability. The reliability of key technologies in 3D integration with these representative platforms are summarized in the paper to address the feasibility of 3D IC in mass production, which could be the guidelines for future development and applications of 3D integration technology.

Innovative through-silicon-via formation approach for wafer-level packaging applications

Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system-in-packaging and wafer-level packaging applications. Among several available TSV formation methods, Bosch deep reactive ion etching (DRIE) is widely used because it enables the fabrication of TSVs with almost any diameter, from the submicrometer level to hundreds of micrometers. However, the high cost of Bosch DRIE makes it uneconomical for industrial production. We present a novel wafer-level TSV formation approach that is effective and cost-efficient. The proposed method integrates a diode-pumped solid-state ultraviolet nanosecond pulsed laser and rapid wet chemical etching. The former is effective in drilling through 400 µm thick silicon wafers and the latter is used for removing the unwanted heat-affected zone, recast layer and debris left after drilling. Experimental results demonstrate that the combined approach effectively eliminates the unwanted material formed by nanosecond laser pulses. Furthermore, this approach has a significant cost advantage over Bosch DRIE. In summary, the proposed approach affords superior TSV quality, higher TSV throughput and lower cost of process ownership than Bosch DRIE. These advantages could provide the necessary impetus for rapid commercialization of the several high-density fabrication methodologies that depend on TSVs.

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

In order to realize the manufacturing and cost benefits of bumpless wafer-on-wafer (WOW) technology for the advent of 3D stacked devices, creation of through silicon vias (TSV) spanning all layers of the fully formed semiconductor device must be realized. This is particularly challenging for logic devices with multiple interconnect layers comprised of various dielectric films including low k. This paper, for the first time, demonstrates the manufacture of TSV's through such device's multi-layered dielectric and silicon, simultaneously.

Failure Analysis and Reliability of 3D Integrated Systems

Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines. A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT. The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from −55 C ° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering. The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT's TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail.

TSV Resist and Residue Removal

3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are numerous technical papers and presentations on the etching and filling of these vias, however the process for cleaning is seldom mentioned. Historically, after reactive ion etching (RIE), cleaning is accomplished using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution-based post etch residue remover. However, in the case of TSV formation, deep reactive ion etching (DRIE) is used to create the vias. A byproduct of this etching process is the formation of a fluorinated passivation layer, often referred to as a fluoropolymer. The fluoropolymer is not easily removed using traditional post etch residue removers, thus creating the opportunity for new and improved formulations and processes for its removal. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using Dynastrip™ AP7880™-C, coupled with a megasonic final rinse provides clean results for high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors

One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at &amp;lt;200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage &amp;gt;8 MVcm−1 and leakage current &amp;lt;1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls. Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.

Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package

Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias.

High-Density Through Silicon Vias for 3-D LSIs

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.