Advanced through silicon vias for hybrid pixel detector modules

Abstract

The through-silicon via (TSV) technology offers high-density vertical stacking of integrated circuits, providing a smaller and simpler structure, whilst increasing connectivity and performance. In High-Energy Physics (HEP) experiments, via-last TSVs are exploited to build low material modules for the upgrades of pixel detectors at the High Luminosity LHC (HL-LHC). In order to prove this concept a versatile via-last TSV process is being developed using ATLAS FE-I4 pixel read-out wafers. It allows modules being operated from the chip backside using the TSV-enabled connectivity. The current status of this development is discussed and results of the TSV formation process and the fabrication of the redistribution layer (RDL) on the ATLAS FE-I4 wafers are shown together with electrical results of the first read-out chips while operated via TSVs and RDLs. Another emphasis of this R&D is the industrial benefit, especially for small and medium companies, which will have access to more affordable and, therefore, competitive option.