Electrical Characterization of CMP-Less Via-Last TSV under Reliability Stress Conditions

Abstract

Via-Last (VL) Through Silicon Via (TSV) is being pursued for its added benefits of process flow simplicity, lower cost and integration flexibility. A novel, CMP-less VL TSV integration flow has been reported previously. Based on cost model analysis, ~9% TSV cost reduction can be achieved by elimination of the Cu Chemical Mechanical Polishing (CMP) process. In addition, it enables applications that requires fine RDL line/space. This paper discusses the electrical characterization of conventional and CMP-less VL TSV before and after thermal stressing. Electrical measurements (on resistance and leakage current) are first performed on the VL TSV samples fabricated using both integration schemes at time zero. The VL TSV samples are then subjected to thermal stress condition of -400C to 1250C for 250 cycles before repeating the electrical measurements. TSV resistance and leakage current data, before and after thermal stress, shows little difference in terms of electrical performance between conventional and CMP-less VL TSVs.