Design space exploration for robust power delivery in TSV based 3-D systems-on-chip

Abstract

3-D integration technologies offer significant advantages to develop multiprocessor systems-on-chip with embedded memory. Reliable power distribution is a challenging issue in these systems due to multiple planes and through silicon vias (TSVs). The two primary TSV technologies, via-first and vialast, have been evaluated for power delivery in a 32 nm 3D system with eight memory planes and one processor plane. Since the impedance characteristics of via-first and via-last based TSVs are significantly different due to distinct filling materials and dimensions, the power distribution network in each case exhibits different design requirements. A valid design space is identified for both cases. Despite the low parasitic resistance of a via-last TSV, a power network based on via-last TSVs produces signal routing blockages. Furthermore, via-last TSVs exhibit high inductive behavior, producing a non-monotonic design space. It is demonstrated that via-first TSVs can satisfy the power supply noise at the expense of 7.5% additional area as compared to via-last TSVs.