Si Etching for TSV Formation

Abstract

Through silicon via (TSV) technology is being considered as a promising technology in three-dimensional packaging, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. The Bosch process is the most widely utilized DRIE process for producing high-aspect ratio TSVs. The primary steps in the Bosch process are silicon isotropic etching and wall passivation in sequential cycles. SF6 is used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. Controlling the scallop is key good insulation and metal coverage. In this study, TSVs with scallops smaller than 100nm was obtained by adjusting the flow ratio of SF6 to C4F8 and the cycle time ratio between SF6 and C4F8. Unfortunately this combination leads to the formation of silicon grass at the bottom of the TSV. The addition of O2 during the SF6 etch cycle was found to eliminate the occurrence of Si grass. Finally, TSVs with low scallop were consistently obtained without Si grass by using SF6/O2 during the etch cycle and C4F8 during the passivation cycle.