Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

Abstract

In order to realize the manufacturing and cost benefits of bumpless wafer-on-wafer (WOW) technology for the advent of 3D stacked devices, creation of through silicon vias (TSV) spanning all layers of the fully formed semiconductor device must be realized. This is particularly challenging for logic devices with multiple interconnect layers comprised of various dielectric films including low k. This paper, for the first time, demonstrates the manufacture of TSV's through such device's multi-layered dielectric and silicon, simultaneously.