Abstract
In this paper, Cu–Sn stack bonding technology for 3D-TSV packaging was described; some key technologies such as TSV (through silicon via) formation, silicon wafer thinning, TSV electroplating and Cu–Sn multilayer stack bonding were introduced. First of all, some sample chips with TSV and Cu–Sn bonding pads were fabricated for stacking. Then, two kinds of stack bonding experiments with or without TSV were carried out, respectively. 3-die, 7-die, and 10-die stacks were bonded and assembled. Finally, the bonding strengths of 3D-TSV stacking were characterized by shear test and tensile test, and also the electrical properties, thermal properties and corrosion resistance of stacked module. All the test results suggested that the reliable stack bonding technology can be used for 3D integration applications.
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