3D TSV processes and its assembly/packaging technology

Abstract

Demand for Through Silicon Via (TSV) is being driven by the need for 3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging using the z-axis TSV stacking concept has been and continues to be investigated by a number of semiconductor manufacturers and research institutes and is believed to be one of the most promising technologies. There is a growing interest in the development and application of this new chip stacking approach to existing and future devices. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes. Applications have to be well understood and integrated in order to successfully be applied. This paper addresses TSV fabrication processes as well as TSV assembly and packaging. The key TSV processes to be discussed in this paper are TSV formation, thin wafer handling, Cu plating and wafer thinning/CMP to form 3D interconnects. Characterization, advantages and challenges associated with each of these process steps and various TSV technologies will be presented. Packaging challenges and experimental results will be presented for CTW (Chip-to-Wafer) bonding with ultra fine pitch microbump interconnections.