Threshold Voltage Mismatch Research Articles

An asymmetrically controlled sense amplifier with boosted sensing voltage difference for low-voltage and high-density DRAM

The transistor threshold voltage mismatch and sensing noise are larger with technology scaling, while the sensing voltage difference of bit-line sense amplifier becomes smaller. Though various offset calibration techniques have been adopted in bit-line sense amplifiers to compensate for the offset mismatch, sensing offset and noise are still critical issues to limit the sensing margin. This brief proposes a bit-line sense amplifier with asymmetrically controlled isolation devices to solve the sensing offset and sensing noise problems simultaneously. Being biased to the calibration point, the target inverter acts as an amplifier with a large voltage gain (AV) to boost the sensing voltage difference, making the sensing voltage difference of the proposed amplifier be 1 + |AV| times that of a conventional latch-type sense amplifier. And the pre-sensing operation performs in parallel with boosting to suppress the sensing noise, without additional time and area consumption. By offset calibration and voltage difference boosting techniques, the proposed design has suppressed the sensing noise and enhanced the sensing margin. All designs are implemented on SMIC 40-nm technology, operating at a supply voltage of 1.05 V or less. The proposed sense amplifier has reduced the standard deviation of the decision threshold voltage to 0.62× and improved the sensing yield by 17.96%. In addition, the boosted sensing voltage difference speeds up the sensing stage, compensating for the pre-sensing time by 36%. Keeping the same number of transistors as the prior offset mismatch calibration sense amplifier, the proposed sense amplifier with improved sensing margin is suitable for low-voltage and high-density DRAM.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage.

With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical VT variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin.

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet’s sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

Magnetic Integration Into a Silicon Carbide Power Module for Current Balancing

Threshold-voltage mismatch among paralleled dies leads to unbalanced turn- on peak currents and switching energies, thus degrading reliability. A passive method employing inversely coupled inductors of tens of nH and drive-source resistors reduces current unbalance. An integrated design of the coupled inductors is required to facilitate their practical use in a power module. A layout to achieve inverse coupling, high coupling coefficient, and low voltage stress, magnetic materials suitable for operation at tens of MHz, and high current rating of tens of amperes with small magnetic core are challenging for its implementation. A module with integrated coupled inductors that achieve inverse coupling by utilizing the copper trace of the substrate and bond wires, size comparable to the silicon carbide die, coupling coefficient higher than 0.98, tens of nH operating at tens of MHz, and current rating of tens of amperes was designed, fabricated, and validated in this work. The coupled inductors with magnetic material of low-temperature cofired ceramics are compatible with existing packaging technology for module fabrication. Effectiveness on reducing transient-current mismatch at various input voltages, load currents, and gate resistances was verified by experiments. Compared with the baseline module resembling commercial modules, the module with integrated coupled inductors reduces current unbalance from 36% to 6.4% and turn- on energy difference from 28% to 2.6% while maintaining the same total switching energy and negligible change of voltage stress.

0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array

This brief presents a subthreshold voltage divider based strong physical unclonable function (PUF). The PUF derives its uniqueness from random mismatch in threshold voltage in an inverter with gate and drain shorted and biased in subthreshold region. The nonlinear current-voltage relationship in subthreshold region also makes the proposed PUF resistant to machine learning (ML) based attacks. Prediction accuracy of PUF response with logistic regression, support vector machine (SVM) and multi-layer perceptron (MLP) is close to 51%. A prototype PUF fabricated in 65nm consumes only 0.3pJ/bit, and achieves the best combination of energy efficiency and resistance to ML attacks. The measured inter and intra hamming distance (HD) for the PUF are 0.5026 and 0.0466 respectively.

A 20F2 Area-Efficient Differential NAND-Structured Physically Unclonable Function for Low-Cost IoT Security

A differential NAND-structured physically unclonable function (PUF) with 20F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area per bit is proposed for cost-effective Internet of Things applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized nMOS transistors by effectively amplifying threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation, which is desired for stability, and faster operation than leakage current-based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs.

Fin Angle Variation Oriented Threshold Voltage Model for a FDSOI FinFET

To support the current level of integration beyond 22 nm, the FinFET architecture is introduced with the expectation of greater levels of device matching. An additional mechanism, arising from charges present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute significantly to transistor mismatch. As the fin is being tapered, quantum mechanical effects come into scene, which contribute to threshold voltage mismatch in the device. This atomic level jogs arise along the taper length of the device can introduce a significant amount of unpassivated charges along the fin. We show that including this mechanism can improve the quantitative understanding of mismatch in FinFETs. For this purpose, an ideal FDSOI FinFET with various fin angles are considered. The existing models are not in agreement with these effects to understand the device better. An analytical model is necessary to relate this mismatch due to differences in threshold voltages with fin angle variation which helps to analyse the influence of the FinFET sidewall inclination angle on the threshold voltage. Threshold voltage and intrinsic trap variations for various fin angles and surface charge densities are measured for analytical study. An optimized threshold voltage equation including the effects of quantum mechanism and channel reduction is developed. The simulations are done through a 3D TCAD simulator Atlas Silvaco and validation of model has done in MATLAB tool.

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits

Calibration of Floating-Gate SoC FPAA System

We present a calibration flow for a large-scale floating-gate (FG) system-on-chip field programmable analog array. We focus on characterizing the FG programming infrastructure and hot-electron injection parameters, MOSFET parameters using the EKV model, and calibrating digital-analog converters and analog-digital converters. In addition, threshold voltage mismatches on FG devices due to their indirect structure are characterized using on-chip measurement techniques. The calibration results in enabling a digital approach, where a design can be programmed without having to deal with the local and global mismatches, on a reconfigurable analog system. This paper shows the results of a compiled nonlinear classifier block comprising a vector-matrix-multiplier and a winner-takes-all on three different calibrated chips.

A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch

This brief presents a foreground calibration technique for current source mismatch that is insensitive to temperature variations. Two calibration digital-to-analog converters (CAL DACs) provide correction currents to compensate two current source mismatch components caused by the threshold voltage mismatch and the current factor mismatch. Each CAL DAC has the same temperature dependence as its corresponding mismatch component. The sum current of the two CAL DACs automatically tracks the temperature variations of the current source mismatch with no need for temperature information. To obtain the CAL DAC input codes, two different bias current settings are used instead of calibrating at two separate temperatures. This scheme significantly reduces the calibration time and cost. A 16-bit DAC with this calibration technique is fabricated in a 65-nm CMOS process. The measurement results show that the matching of the most significant bit currents is improved from intrinsic 12 to 16 bits across the temperature range from −40 °C to 85 °C. The proposed calibration technique achieves superior temperature stability compared to the previously published schemes.

A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing

With continued CMOS technology scaling down, transistors exhibit higher degrees of variation and mismatch, resulting in a larger offset voltage. A large offset voltage will enlarge bitline swing, increasing dynamic power consumption during a read operation and degrading the sensing decision correct rate and operation speed. Thus, the offset voltage is the most critical metric for static random access memory sense amplifiers (SAs), mainly arising from transistor threshold voltage mismatch. Here we propose an offset-cancelling technique with digitized multiple body biasing. In this scheme, SA transistor threshold voltage mismatch is compensated by adjusting the body bias voltage digitally and repeatedly. Simulation results in 130-nm CMOS technology show that the proposed calibration technique can reduce the standard deviation of the offset voltage by over four times comparing to a conventional SA, with about 6.5% and 1.6% area power overhead of a 6-kbit prototype chip introduced.

Channel Profile Design of $\text{E}\delta $ DC MOSFET for High Intrinsic Gain and Low $V_{T}$ Mismatch

In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel ( $\text{E}\delta $ DC) MOS transistor so that the intrinsic gain ( $A_{v}$ ) is high and the threshold voltage ( $V_{T}$ ) mismatch is low. Analytical study shows that a tradeoff relation exists between low $V_{T}$ mismatch and high $A_{V}$ with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized $\text{E}\delta $ DC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized $\text{E}\delta $ DC transistor with respect to the chosen objectives is clearly explained.

High speed switched-current memory cell with very low offset and charge injection errors

In this paper a high speed class AB switched-current memory cell is presented. Memory transistors have been designed in triode region in order to reduce the threshold voltage mismatch and clock feed-through errors. Also a modified Flipped Voltage Follower (FVF) circuit is used to cancel charge injection error. Besides, this cell consists of a new common-mode feedforward (CMFF) circuit which attenuates the common mode components and improves offset error at output. Furthermore, a coupled differential (CDR) memory cell (MC) is used to eliminate the clock feedthrough (CFT) error considerably. All of the presented circuits have been designed by using TSMC 0.18μm process parameters and simulated in HSPICE. Simulation results show that maximums of THD, SNR and SFDR at clock frequency of 100MHz and 1MHz as input frequency are –71dB, 71.2dB and 68dB respectively. Obtained results demonstrated considerable improvement in the circuit performance which confirm the excellence of proposed memory cell in comparisons to previous cells.

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$C _{BL}$</tex></formula> ), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V _{THC}$</tex> </formula> ), DNSS reduces the cross-layer <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$C _{BL}$</tex></formula> -mismatch by 41%, LA-PV-R using various program-threshold-voltages ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$V _{THP}$</tex></formula> ) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVG NAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V _{THP}$</tex></formula> between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.

A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.

The existing ISFET-based DNA sequencing detects hydrogen ions released during the polymerization of DNA strands on microbeads, which are scattered into microwell array above the ISFET sensor with unknown distribution. However, false pH detection happens at empty microwells due to crosstalk from neighboring microbeads. In this paper, a dual-mode CMOS ISFET sensor is proposed to have accurate pH detection toward DNA sequencing. Dual-mode sensing, optical and chemical modes, is realized by integrating a CMOS image sensor (CIS) with ISFET pH sensor, and is fabricated in a standard 0.18-μm CIS process. With accurate determination of microbead physical locations with CIS pixel by contact imaging, the dual-mode sensor can correlate local pH for one DNA slice at one location-determined microbead, which can result in improved pH detection accuracy. Moreover, toward a high-throughput DNA sequencing, a correlated-double-sampling readout that supports large array for both modes is deployed to reduce pixel-to-pixel nonuniformity such as threshold voltage mismatch. The proposed CMOS dual-mode sensor is experimentally examined to show a well correlated pH map and optical image for microbeads with a pH sensitivity of 26.2 mV/pH, a fixed pattern noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/s. A dual-mode CMOS ISFET sensor with suppressed FPN for accurate large-arrayed pH sensing is proposed and demonstrated with state-of-the-art measured results toward accurate and high-throughput DNA sequencing. The developed dual-mode CMOS ISFET sensor has great potential for future personal genome diagnostics with high accuracy and low cost.

Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective

The effect of ultra low operating temperature on mismatch among identically designed Silicon-on-Sapphire CMOS devices is investigated in detail from a circuit design view point. The evolution of transistor matching properties for different operating conditions at both room and 4.2K temperature are presented. The statistical analysis reveals that mismatch at low temperature is effectively unrelated to that at room temperature, which disagrees with previously published literature. The measurement data was used to extract key transistor parameters and the consequence of temperature lowering on their respective variance is estimated. We find that standard deviation of the threshold-voltage mismatch deteriorates by a factor ∼2 at 4.2K temperature. Similar to room temperature operation, mismatch at 4.2K is bias point dependent and the degradation of matching at very low temperature depends to some extent on how the bias point shifts upon cooling.

Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch

In this brief, threshold voltage mismatch of fully integrated n-type FinFETs based on a gate-first process was studied experimentally. Significantly improved threshold voltage mismatch due to undoped FIN body was confirmed with the experimental data. By comparing mismatch values of thin- and thick-oxide nMOS, we found that factors, which do not scale with gate oxide thickness, including line edge roughness and metal-gate granularity (MGG), can explain ~ 60% of total mismatch of thin-oxide devices. Moreover, we report a convex shape of threshold voltage mismatch following the increase of the number of FINs and propose a possible explanation of the abnormal behavior. Due to channel width quantization, two competing contributors impact mismatch: as FIN number becomes smaller mismatch due to MGG likely play an important role which increases threshold voltage mismatch, whereas FIN number becomes larger, systematic variation becomes the main factor, which also increases threshold voltage mismatch.

Fault Models and Test Methods for Subthreshold SRAMs

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.

Implementation of an Efficient SRAM for Ultra-Low Voltage Application Based on ST for Better Read Stability and Write Ability

Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read- stability as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were done using DSCH and Microwind. Index Terms: read stability, write ability, Schmitt trigger. I. Introduction PORTABLE electronic devices have extremely low power requirement to maximize the battery lifetime. Various device-/circuit-architectural-level techniques have been implemented to minimize the power consumption. Supply voltage scaling has significant impact on the overall power dissipation.With the supply voltage reduction, the dynamic power reduces quadratically while the leakage power reduces linearly (to the first order). However, as the supply voltage is reduced, the sensitivity of circuit parameters to process variations increases. This limits the circuit operation in the low-voltage regime, particularly for SRAM bitcells employing Minimum-sizedtransistor. These minimum geometry transistors are vulnerable to interdie as well as intradie process variations. Intradie process variations include random dopant fluctuation (RDF) and line edge roughness (LER). This may result in the threshold voltage mismatch between the adjacent transistors in a memory bitcell, resulting in asymmetrical characteristics. The combined effect of the lower supply voltage along with the increased process variations may lead to and increased memory failures such as read-failure, hold-failure, write- failure, access-time failure. Moreover, it is predicted that embedded cache memories, which are expected to occupy a significant portion of the total die area, will be more prone to failures with scaling.