Abstract

With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical VT variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin.

Highlights

  • Effects on Dynamic random access memory (DRAM) Sense AmplifierArtificial intelligence (AI) and 5G networks are emerging as major topics in information technology (IT)

  • The V T s of sense amplifier (SA) in a die follow a Gaussian distribution. Because it has been proven by previous studies that the major factor that affects the offset voltage is ∆V T, we considered only σ(V T ) and

  • Each dies in a wafer is predicted as follows

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Summary

Introduction

Artificial intelligence (AI) and 5G networks are emerging as major topics in information technology (IT). These applications require high-density and low-power memory. Dynamic random access memory (DRAM) can play an important role, owing to its fast switching speed, low bit cost, and high memory density [1]. The cell part consists of a cell transistor acting as a switch and a cell capacitor storing charge.

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