Fin Angle Variation Oriented Threshold Voltage Model for a FDSOI FinFET

Abstract

To support the current level of integration beyond 22 nm, the FinFET architecture is introduced with the expectation of greater levels of device matching. An additional mechanism, arising from charges present at points of disturbance in the silicon lattice in tapering and wavering fins is shown to contribute significantly to transistor mismatch. As the fin is being tapered, quantum mechanical effects come into scene, which contribute to threshold voltage mismatch in the device. This atomic level jogs arise along the taper length of the device can introduce a significant amount of unpassivated charges along the fin. We show that including this mechanism can improve the quantitative understanding of mismatch in FinFETs. For this purpose, an ideal FDSOI FinFET with various fin angles are considered. The existing models are not in agreement with these effects to understand the device better. An analytical model is necessary to relate this mismatch due to differences in threshold voltages with fin angle variation which helps to analyse the influence of the FinFET sidewall inclination angle on the threshold voltage. Threshold voltage and intrinsic trap variations for various fin angles and surface charge densities are measured for analytical study. An optimized threshold voltage equation including the effects of quantum mechanism and channel reduction is developed. The simulations are done through a 3D TCAD simulator Atlas Silvaco and validation of model has done in MATLAB tool.