An asymmetrically controlled sense amplifier with boosted sensing voltage difference for low-voltage and high-density DRAM

Abstract

The transistor threshold voltage mismatch and sensing noise are larger with technology scaling, while the sensing voltage difference of bit-line sense amplifier becomes smaller. Though various offset calibration techniques have been adopted in bit-line sense amplifiers to compensate for the offset mismatch, sensing offset and noise are still critical issues to limit the sensing margin. This brief proposes a bit-line sense amplifier with asymmetrically controlled isolation devices to solve the sensing offset and sensing noise problems simultaneously. Being biased to the calibration point, the target inverter acts as an amplifier with a large voltage gain (AV) to boost the sensing voltage difference, making the sensing voltage difference of the proposed amplifier be 1 + |AV| times that of a conventional latch-type sense amplifier. And the pre-sensing operation performs in parallel with boosting to suppress the sensing noise, without additional time and area consumption. By offset calibration and voltage difference boosting techniques, the proposed design has suppressed the sensing noise and enhanced the sensing margin. All designs are implemented on SMIC 40-nm technology, operating at a supply voltage of 1.05 V or less. The proposed sense amplifier has reduced the standard deviation of the decision threshold voltage to 0.62× and improved the sensing yield by 17.96%. In addition, the boosted sensing voltage difference speeds up the sensing stage, compensating for the pre-sensing time by 36%. Keeping the same number of transistors as the prior offset mismatch calibration sense amplifier, the proposed sense amplifier with improved sensing margin is suitable for low-voltage and high-density DRAM.