Test Vector Generation Research Articles

Automated Test Case Generation for Chip Verification Using Deep Reinforcement Learning

This paper presents a novel automated test case generation framework leveraging deep reinforcement learning (DRL) for chip verification. The framework addresses the growing complexity in modern chip designs where traditional verification methods must help achieve comprehensive coverage efficiently. Our approach implements a custom deep Q-network architecture optimized for processing coverage feedback and generating test vectors, incorporating an innovative reward mechanism that balances coverage optimization with simulation efficiency. The proposed system features a hierarchical state space representation scheme that captures temporal and spatial aspects of coverage progression, combined with an adaptive training strategy that dynamically adjusts to verification requirements. The framework is evaluated on multiple industrial-scale benchmark designs, demonstrating significant improvements over conventional methods, achieving up to 98.5% functional coverage with a 45% reduction in verification time. The distributed implementation demonstrates near-linear scaling across multiple GPU nodes while maintaining high resource utilization efficiency. Experimental results show that the DRL-based approach outperforms traditional constrained-random and coverage-driven test generation methods across various metrics, including coverage rate, corner case detection, and simulation efficiency. The framework's integration with existing verification workflows and its ability to handle complex design scenarios make it particularly suitable for modern chip verification challenges.

Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding.

Loss-less data compression becomes the need of the hour for effective data compression and computation in VLSI test vector generation and testing in addition to hardware AI/ML computations. Golomb code is one of the effective technique for lossless data compression and it becomes valid only when the divisor can be expressed as power of two. This work aims to increase compression ratio by further encoding the unary part of the Golomb Rice (GR) code so as to decrease the amount of bits used, it mainly focuses on optimizing the hardware for encoding side. The algorithm was developed and coded in Verilog and simulated using Modelsim. This code was then synthesised in Cadence Encounter RTL Synthesiser. The modifications carried out show around 6% to 19% reduction in bits used for a linearly distributed data set. Worst-case delays have been reduced by 3% to 8%. Area reduction varies from 22% to 36% for different methods. Simulation for Power consumption shows nearly 7% reduction in switching power. This ideally suggest the usage of Golomb Rice coding technique for test vector compression and data computation for multiple data types, which should ideally have a geometrical distribution.

Finding the longest delay paths for the array-form multipliers using a genetic algorithm

Traditional digital multipliers are often designed in array forms or other variants. Timing of array-form multipliers can be analyzed by static timing analysis (STA), but the obtained timing result is conservative and pessimistic. Although statistical static timing analysis (SSTA) can partly solve the pessimism, it still does not generate test patterns for those near-to-longest delay paths. Finding near-to-longest delay paths can be helpful to designing error tolerant circuits, with which aggressive timing (with timing violation) can be exploited. In such design scenarios one should find test vectors to activate those near-to-longest delay paths in order to further run SPICE-precision diagnose on those potential timing violating critical paths. Test vector generation for such a testing problem is essentially an exhaustive enumeration problem when dealing with different forms of array multipliers. However, large size multipliers would result in an extremely large enumeration space for finding the longest delay path (LDP) test vectors. Currently there is no deterministic method that can guarantee to find test vectors for exact LDPs of a large size multiplier. Only very few research papers have addressed this problem, proposals are limited to heuristic methods without guarantee of finding the LDPs with the testing vectors. This paper investigates the potential of a genetic algorithm (GA) for searching the extensive test pattern space. By a fine design of GA, experimental running shows that a combination of well tuned evolutionary operators does empower the possibility of finding the LDPs for a set of moderate size carry-save adders (CSA) multipliers with the wordlength (WL) up to 25 bits on a plain laptop computer. Statistical properties of the proposed GA are examined.

A synthetic cardiac episode generator for explainable, pathology based action potential using heuristic polynomial signatures

Synthetic generation of biophysical signals caters to diverse applications of test vectors generation, exploration, data augmentation and machine learning training. Arrhythmiator, our contribution is a Python framework to generate synthetically, action potential for explain-ability and explore-ability of pathology (Arrhythmia) influenced cardiac episodes. In this work, we address the problem of large cardiac data-sets need, for deep learning models which are hindered by privacy laws by synthetic generation. We have addressed the problem of explainable computations, multi-scale, by virtue of novel stack sliced polynomial signatures, piece-wise linear and application context driven fitting/filtering in algorithmic framework. To account the problem of lack of standardised pathology specifications we developed PDL (Pathology descriptive language) portal which can be customised. We also addressed the challenge of high turnaround development cycle, inter-operate-ability computation issue by developing a single unified Python framework. To address computational costs, we leverage domain-specific heuristics through sliced state space control algorithms and a constant temporal resolution. We demonstrate the utility of our framework by generating two cases of Tachycardia, one influenced by sodium pump inhibition of spontaneous diastolic depolarisation (SDD) slope and other by ischaemic episode causing maximum diastolic depolarisation (MDP) shift. The concept of the pacemaker hierarchy is encompassed by developing pathology explainable computation as a structure (PECS). We showcase the flexibility and explore-ability of our framework through ease of filter connect profile plug-ins for action potential states upstroke and plateau. We validated the generated waveforms by developing trace and debug algorithms and a reference deviation score which marks the pathology influence. The validator module is a vectored attribute of action potential based on state space control algorithms.

Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity

Hardware Trojans (HTs) are small circuits intentionally designed by an adversary for harmful purposes. These types of circuits are extremely difficult to detect. An HT often requires some specific signals to activate, which are almost impossible to discover. For this reason, test generation for side-channel analysis has gained significant attention in recent times and does not require HT activation. Such test generation techniques aim to generate a large amount of switching activity inside the HT circuit, increasing transient current measurement. However, such methods suffer from either long runtime or reliable results. In this work, a test generation technique is proposed based on the relative switching activity of the circuit to overcome the limitations of the existing works. Initially, the proposed technique measures the impact of each input on rare nets individually using random vector simulation. Potent inputs are selected to obtain a new set of test vectors that provide high relative switching inside a circuit. The proposed method is applied on 11 different ISCAS and 3 ITC 99 benchmark circuits. Experimental results endorse the efficacy of the proposed method outperforming traditional Hamming distance-based re-ordering techniques (up to 20×) while requiring a small runtime.

Research on Low Power BIST Based on LFSR Reseeding

With the increasing scale and complexity of the internal circuit, the function of the chip is more powerful, but it will bring serious problems to the test of the chip. The internal power consumption of the chip in the test mode is much higher than that in the normal working mode, especially in the process of built-in self-test, the excessive power consumption will damage the circuit under test and lead to the failure of the chip. The low power test vector generation technology reduces the test power by preprocessing the test vector set. However, the modification of the test vector set results in the low failure coverage in the test process. LFSR replaying technology is a common method of generating test vectors in built-in self-test. It can improve the coverage of test faults by loading test vector seeds into linear feedback shift register. However, while improving the fault coverage, the technology will generate high test power consumption in the circuit under test. In design for testability (DFT), it is a hot topic to generate low-power test vectors by combining LFSR reseeding technology with low-power test vector generation technology. Aiming at the problem of high power consumption caused by test vectors in built-in self-test, this paper proposes a low power test vector generation method based on LFSR reseeding. On the basis of studying the influence of test vector on dynamic test power consumption, the linear correlation between test vector seed and test vector is analyzed deeply. A model of dynamic test power consumption optimization based on Hamming distance sorting test vector seed is proposed to realize the design of low-power test vector seed generation algorithm. Combined with LFSR reseeding technology, a low-power test vector generator based on test vector seed sorting is designed. The simulation design of test vector generator is based on ISCAS85 and ISCAS89. The experimental results show that the total number of test vector seed storage bits is reduced by 64.39%, the average fault coverage is 97.42%, the average area overhead is 4.32%, and the dynamic test power consumption is reduced by 44.21%. Compared with other schemes, the proposed low-power test vector generation technology based on LFSR reseeding has some comprehensive advantages in reducing the number of seed storage bits, improving fault coverage, reducing circuit area overhead and reducing power consumption.

On-chip test vector generation and downsampling for testing RSFQ circuits

An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

A reconfigurable test method based on LFSR for 3D stacking integrated circuits

The specificity of the 3D integrated circuit and the changes in the design integration flow bring many new problems to the test process, such as reducing the controllability of the test and increasing the test cost. To address these problems, this paper proposes a low-power hybrid test scheme based on multiple reconfigurable linear feedback shift register(LFSRs) for 3D integrated circuit, which can reuse the test vector generator of the pre-binding test phase in the in-binding and post-binding test phase, reconfiguring a new test vector generator with lower test cost. Compared with the method of using the linear feedback shift register(LFSR) of each layer circuit independently as the test vector generator of the whole circuit in the in-binding test phase, the scheme in this paper can effectively utilize the original LFSR of each layer circuit and reduce the area overhead; the reconfigured 3D-LFSR can obtain better test data compression effect and lower test power consumption, improve test efficiency and reduce test time. Experiments have shown a 5% improvement in average test data compression, 53.1% and 9.6% reduction in average and peak power consumption respectively, 28% reduction in test area and 19.6% reduction in test time.

RS-LDPC stochastic joint decoding algorithm

Due to complexity issues, low-density parity-check (LDPC) codes often use a partial parallel decoding architecture, which cannot easily meet the requirements of high-speed and ultra-high-speed applications. Conversely, the Reed-Solomon (RS) codes often use hard decision decoding algorithms in existing decoding schemes. Therefore, there is room for further optimization in the complexity and performance of concatenated RS -LDPC decoding. In this paper, we propose an RS-LDPC stochastic joint iterative decoding algorithm based on the principle of stochastic computing. This algorithm inherits the advantages of the low complexity of stochastic LDPC decoders and the feature of stochastic RS decoding algorithms, which can use hard decoders. Meanwhile, the decoding performance is improved through the joint iterative decoding architecture. In this respect, we design a test-vector generation method based on LDPC probability values and adopt a novel additional extrinsic information generation mechanism. Such a mechanism is applied to the structure of the variable nodes of the stochastic LDPC decoder. The simulation results show that at a bit error rate of $10^{-6}$, the proposed algorithm can obtain a gain of 0.3 dB as compared with the RS-LDPC cascaded decoding scheme using floating-point belief propagation and Berlekamp -Massey hard decision decoding algorithm. Its implementation complexity is the complexity of a stochastic LDPC decoder and several RS hard decoders. The decoding latency is determined by the latency of the stochastic LDPC decoder. Therefore, the joint iterative decoding algorithm proposed in this paper has a very good application value.

Adjustable PRPG for Low Power Test Patterns

As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C.

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS’85 benchmark design as an example.

An Efficient Technique to Detect Stealthy Hardware Trojans Independent of the Trigger Size

Detecting Hardware Trojans (HTs) in digital circuits might be a challenging problem due to the stealthy nature of these malicious unwanted guests. The trigger part which is supposed to activate the Trojan under exceptional conditions, is often inserted at rare–switched nets of the design to hide them from usual verification tests mechanisms. Existing Trojan detection methods straggle in detecting modern Trojans which mostly have exploit multiple-input triggering parts to drive small payloads. Addressing such multiple-input triggering circuitries needs wise activation mechanisms with a reasonable time-complexity to serve as a feasible solution for large commercial designs. In this paper we present an algorithm which analyses fan-in and fan-out cones along with the Hardware Trojan susceptibility of the most suspicions nets of gate-level designs to find subsets of them which could most probably activate an inserted HT. Then a fast test vector generation algorithm is proposed to excite as many susceptible nets as possible for achieving the multiple nets excitation requirement. The results of applying the proposed algorithms on the TRIT and trust-hub benchmark suites show an average of 89% HT detection coverage while the required maximum run time is much smaller than the previous state of the art methods.

An Integrated Framework for Application Independent Testing of FPGA Interconnect

This paper presents a FPGA interconnect test configuration generation strategy for application-independent testing using Satisfiability (SAT). The technique generates all possible path configurations for the interconnect to obtain full coverage of all interconnect resources. The integrated testing approach is proposed which generates test vectors and path configurations in a single phase, thus obtaining a significant reduction in the number of test configurations needed to test the circuit. To generate test configurations, constraints have been designed using SAT. The proposed technique targets open and short faults in the interconnect resources. Test configurations have been generated for different FPGA architectures. The objective of the proposed approach is to minimize the number of configurations without reducing the fault coverage.

A compressive sensing algorithm for hardware trojan detection

Traditionally many fabless companies outsource the fabrication of IC design to the foundries, which may not be trusted always. In order to ensure trusted IC’s it is more significant to develop an efficient technique that detects the presence of hardware Trojan. This malicious insertion causes the logic variation in the nets or leaks some sensitive information from the chip, which reduces the reliability of the system. The conventional testing algorithm for generating test vectors reduces the detection sensitivity due to high process variations. In this work, we present a compressive sensing approach, which can significantly generate optimal test patterns compared to the ATPG vectors. This approach maximizes the probability of Trojan circuit activation, with a high level of Trojan detection rate. The side channel analysis such as power signatures are measured at different time stamps to isolate the Trojan effects. The effect of process noise is minimized by this power profile comparison approach, which provides high detection sensitivity for varying Trojan size and eliminates the requirement of golden chip. The proposed test generation approach is validated on ISCAS benchmark circuits, which achieves Trojan detection coverage on an average of 88.6% reduction in test length when compared to random pattern.

Generation of Reduced Test Vectors for Multiple Stuck at Faults using Genetic Algorithm

As seen in the fabrication of circuits faults free circuits are difficult to obtain, as the manufacturing process is narrowing down, hence finding faults is very essential at the design level to obtain fault free circuits. As seen many of circuits have single and multiple faults, as known many research has been carried out to generate test pattern set that detect MSA faults, here the proposed ATPG method makes use of test patterns of single stuck at faults to identify MSA faults. This paper implements a method for multiple faults, generated test patterns for multiple faults has proved to be efficient by adapting a complex method of the order 3n-1 for ‘n’ lines reduced test pattern sets were obtained. This method overcomes the limitations of continuous searching algorithms, as the initial value of population size was randomly set to produce test vectors for MSA faults. The CPU processing time is very less compared to other ATPG techniques. To understand the working of the proposed methodology, we have performed an analysis by considering the ISCAS Benchmark circuits, to which the proposed ATPG method is applied, which gives the complete test vector (pattern) generation for MSA faults in the limited interval of runtime which also covers the test pattern sets for single faults.

Survey on automated symbolic verification and its application for synthesising cyber‐physical systems

Dependency on the correct operation of embedded systems is rapidly growing, mainly due to their wide range of applications. Their structures are becoming more complex and currently require multi-core processors with scalable shared memory, signal-processing pipelines, and sophisticated software modules to meet increasing computational power, flexibility demands. Additionally, interaction with real-world entities and modern communication capabilities further enhance the mentioned features and give rise to the embedded and cyber-physical systems (ECPS). As a consequence, the reliability of ECPS becomes a key issue during system development. Generally, state-of-the-art verification methodologies for ECPS generate test vectors and use assertion-based verification and high-level processor models, during simulation; however, new challenges arose, such as need for meeting time and energy constraints, handling concurrent software, evaluating implementation-structure choices, ensuring correct system behavior together with physical plants, and supporting new software architectures and legacy designs. This survey deals with the mentioned issues, reviews related literature, and discusses recent advances in symbolic model checking techniques and their applications to control synthesis. Additionally, challenges, problems, and recent advances to ensure correctness and timeliness, regarding ECPS, are discussed. Reliability issues, when developing ECPS, are then considered, as a prominent verification and synthesis application for achieving correct-by-construction systems.

Test pattern generation using thermometer code counter in TPC technique for BIST implementation

This paper introduces a newly pattern generation with Test-Per-Clock technique for Built-In-Self-Test implementation. This proposed test vector generation generates Multiple Single Input Change vectors. Each pattern enforced in SIC vector as scan chain. To generate minimal transition sequence of test patterns, a scalable SIC counter and Thermometer Code Counter implemented. The proposed Multiple SIC vector generator is adaptable to both Test-Per-Scan, Test-Per-Clock techniques. This method developed a theory to evaluate MSIC scheme. Survey outcome demonstrates that, applying Multiple SIC test patterns on ISCAS C432 benchmark reduces the power consumption due to uniform distribution and lesser transition generated test patterns.

Symbol-Level Stochastic Chase Decoding of Reed-Solomon and BCH Codes

This paper proposes the symbol-level-stochastic Chase decoding algorithm (S-SCA) for the Reed–Solomon (RS) and Bose–Chaudhuri–Hocquenghem (BCH) codes, which is a soft-input soft-output (SISO) decoder. By the efficient usage of void space between constellation points for $q$ -ary modulations and using soft information at the input of the decoder, the S-SCA is capable of outperforming conventional symbol-level-Chase algorithm (S-CA) with a less computational cost. Since the S-SCA starts with the randomized generation of likely test-vectors, it reduces the complexity to polynomial order and also it does not need to find the least reliable symbols to generate test-vectors. The symbol-level-search bitwise-transmission stochastic Chase algorithm (SSBT-SCA) is also introduced for RS codes over binary phase shift keying (BPSK) transmission that is capable of generating symbol-level test-vectors with reduced complexity and to better mitigate burst errors. Simulation results show that by increasing the number of test-vectors, the performance of the algorithm can asymptotically approach the maximum-likelihood (ML) bound. The S-SCA provides near 2 dB decoding gain in comparison with S-CA for a (31, 25) RS code using 32-QAM, when 1024 test-vectors are used. Furthermore, the algorithm provides near 3 dB additional gain with 1024 test-vectors compared with S-CA that uses 65536 iterations when a (255, 239) RS code is used in an additive white Gaussian noise (AWGN) channel. For the Rayleigh fading channel and the same code, the algorithm provides more than 5 dB gain. Furthermore, for (63, 57) BCH codes and 8-PSK modulation, the proposed algorithm provides 3 dB gain with less complexity.

Test Generation from Boolean Generator for Detection of Missing Gate Faults (MGF) in Reversible Circuit Using Boolean Difference Method

ABSTRACTWith the change in commuting paradigms, the demands in industries have changed accordingly. Consequently, efficient design models and related technologies have evolved as prime driving factors to this cause. In such a scenario, reversible logic design has come out as a prominent future technology which not only provides faster computing platform but also promises energy efficient designs. But it is also very evident that not only the efficient designs play a pivotal role in reliable design models but incorporation of proper testing mechanisms is very important. Further to contribute to this cause, here, in this work we introduce an efficient test vector generation method to detect all type of missing gate faults in reversible circuits. In our proposed scheme, we have explored the Boolean difference property of logic functions for designing a Boolean generator from which fault specific test vectors are computed for different fault models. The test vector generation method is composed of two phases. In first phase, a Boolean generator produces fault specific test vectors and in the second phase, we employ a repeated factoring technique over the generated test set to reduce the test size so that the testing process can be faster. We have tested our developed technique over a large spectrum of benchmarks and an improvement over existing testing works has been registered. We have achieved 71% improvements over test vector count in SMGF, 58% for MMGF and 78% for PMGF.

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed–Solomon Decoding

This paper presents a low-complexity chase (LCC) decoder for Reed–Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide an evidence that the proposed method is suitable for RS codes with different rates and Galois fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at the frame error rate that is equal to 10−6 compared with hard-decision decoding, which is higher than that of an $\eta =5$ LCC. The implementation results in ASIC show that a throughput of 3.6 Gb/s can be reached in a 90-nm process and 29.1XORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gb/s and requires 5085 LUTs.