An Integrated Framework for Application Independent Testing of FPGA Interconnect

Abstract

This paper presents a FPGA interconnect test configuration generation strategy for application-independent testing using Satisfiability (SAT). The technique generates all possible path configurations for the interconnect to obtain full coverage of all interconnect resources. The integrated testing approach is proposed which generates test vectors and path configurations in a single phase, thus obtaining a significant reduction in the number of test configurations needed to test the circuit. To generate test configurations, constraints have been designed using SAT. The proposed technique targets open and short faults in the interconnect resources. Test configurations have been generated for different FPGA architectures. The objective of the proposed approach is to minimize the number of configurations without reducing the fault coverage.